Simulator Modules

The AVR32 Simulator is an instruction set simulator. It does not make any attempt to accurately model the timing behavior of real AVR32 devices. Currently, no peripherals such as I/O ports or USARTs are simulated.

Processor Core

The processor core module supports emulation of all instructions supported by UC3 devices, except the following instructions related to on-chip debugging:

  • retd (return from debug mode)
  • mfdr (move from debug register)
  • mtdr (move to debug register)

Memory

The simulator does not differentiate between flash and SRAM. In effect, this means that all simulated memory can be both read and written. The simulated memory blocks have the same offset and size as those found on the hardware equivalents of the supported parts. The simulator does not model a memory protection unit (MPU) as found on real UC3 devices.

System Registers

The following system registers are simulated:

  • ACBA
  • BEAR
  • COMPARE
  • COUNT
  • CPUCR
  • ECR
  • EVBA
  • SR

Other system registers always read zero.