00001 /*This file has been prepared for Doxygen automatic documentation generation.*/ 00085 #include "board.h" 00086 #include "gpio.h" 00087 #include "scif_uc3l.h" 00088 #include "power_clocks_lib.h" 00089 00092 00093 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK 00094 #define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG // Do not use the AVR32_SCIF_GCLK_DFLL0_REF gc. 00095 #define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN // Mapped on STK600.PORTA.PA6; connector PA6 on AT32UC3L-EK 00096 #define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION 00097 #endif 00098 00099 #if !defined(EXAMPLE_GCLK_ID) || \ 00100 !defined(EXAMPLE_GCLK_PIN) || \ 00101 !defined(EXAMPLE_GCLK_FUNCTION) 00102 # error The generic clock configuration to use in this example is missing. 00103 #endif 00104 00106 #define EXAMPLE_FDFLL_KHZ 24000 00107 #define EXAMPLE_FDFLL_HZ 24000000 00108 00110 #define EXAMPLE_GCLK_FREQ_HZ 12000000 00111 00113 00117 static void local_start_dfll_clock() 00118 { 00119 scif_dfll_closedloop_conf_t DfllConfig; 00120 scif_gclk_opt_t GcConf; 00121 00122 00123 // 1) Configure and start the DFLL main reference generic clock: 00124 // use the undivided RCOSC slow clock as source for the generic clock. The 00125 // generic clock frequency will thus be ~115kHz. 00126 GcConf.clock_source = SCIF_GCCTRL_SLOWCLOCK; 00127 GcConf.diven = OFF; 00128 // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock 00129 // (i.e. the generic clock dedicated to be the DFLL main reference clock). 00130 scif_dfll0_closedloop_mainref_gc_enable(&GcConf); 00131 00132 // 2) Configure and start the DFLL. 00133 // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)) 00134 DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ); 00135 // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the 00136 // DFLL main reference generic clock) 00137 DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_SLOWCLOCK_FREQ_HZ; 00138 // The maxstep value 00139 DfllConfig.maxstep = 1; 00140 scif_dfll0_closedloop_start(&DfllConfig); 00141 } 00142 00143 00148 static void local_start_gc() 00149 { 00150 // Setup gc on DFLL; the target frequency is 12MHz => divide the DFLL frequency 00151 // by 2 (== EXAMPLE_FDFLL_HZ / EXAMPLE_GCLK_FREQ_HZ). 00152 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 00153 EXAMPLE_FDFLL_HZ/EXAMPLE_GCLK_FREQ_HZ); 00154 00155 // Now enable the generic clock 00156 scif_gc_enable(EXAMPLE_GCLK_ID); 00157 00158 /* Assign a GPIO to generic clock output */ 00159 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION); 00160 // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48. 00161 } 00162 00163 00164 00165 /* \brief This is an example that shows how to do the following: 00166 * - generate a high frequency clock (~24MHz) with a DFLL in closed-loop mode 00167 * - set-up a generic clock with a DFLL as a source 00168 * - output the generic clock to GCLK_1_0 00169 * - go into the frozen sleep mode (while still maintaining GCLK output) 00170 * 00171 */ 00172 int main(void) 00173 { 00174 // Generate a high frequency clock (~24MHz) with a DFLL in closed-loop mode 00175 local_start_dfll_clock(); 00176 00177 // Set the division ratio to apply to the main clock to 2 for each clock domain 00178 // so that each clock domain is at 12MHz. 00179 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2); 00180 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_2); 00181 pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2); 00182 // Switch the main clock source to the DFLL. 00183 pm_set_mclk_source(PM_CLK_SRC_DFLL0); 00184 00185 // Set-up a generic clock from a high frequency clock and output it to a gpio pin. 00186 local_start_gc(); 00187 00188 //*** Sleep mode 00189 // If there is a chance that any PB write operations are incomplete, the CPU 00190 // should perform a read operation from any register on the PB bus before 00191 // executing the sleep instruction. 00192 AVR32_INTC.ipr[0]; // Dummy read 00193 00194 // - Go into a sleep mode (while still maintaining GCLK output) 00195 SLEEP(AVR32_PM_SMODE_FROZEN); 00196 00197 while(1); 00198 } 00199