The AVR ONE! supports several hardware interfaces as described in the sections that follow.
The JTAG interface consists of a 4-wire Test Access Port (TAP) controller that is compliant with the IEEE 1149.1 standard. The IEEE standard was developed to provide an industry-standard way to efficiently test circuit board connectivity (Boundary Scan). AtmelŽ AVR devices have extended this functionality to include full Programming and On-Chip Debugging support.
When designing an application PCB which includes an AVR with the JTAG interface, it is recommended to use the pinout as shown in Figure 4.2, “JTAG header pinout”. The AVR ONE! ships with both 100-mil and 50-mil adapters supporting this pinout.
Table 4.1. JTAG pin description
Name | Pin | Description |
---|---|---|
TCK | 1 | Test Clock (clock signal from the AVR ONE! into the target device) |
TMS | 5 | Test Mode Select (control signal from the AVR ONE! into the target device) |
TDI | 9 | Test Data In (data transmitted from the AVR ONE into the target device) |
TDO | 3 | Test Data Out (data transmitted from the target device into the AVR ONE!) |
nTRST | 8 | Test Reset (optional, only on some AVR devices). Used to reset the JTAG TAP controller |
nSRST | 6 | Source Reset (optional) Used to reset the target device. Connecting this pin is recommended since it allows the AVR ONE! to hold the target device in a reset state, which can be essential to debugging in certain scenarios. |
VTref | 4 | Target voltage reference. The AVR ONE! samples the target voltage on this pin in order to power the level converters correctly. The AVR ONE! draws less than 1mA from this pin. |
GND | 2, 10 | Ground. Both must be connected to ensure that the AVR ONE! and the target device share the same ground reference. |
Tip: remember to include a decoupling capacitor between pin 4 and GND.
The JTAG interface allows for several devices to be connected to a single interface in a daisy-chain configuration. The target devices must all be powered by the same supply voltage, share a common ground node, and must be connected as shown in Figure 4.3, “JTAG daisy-chain”.
When connecting devices in a daisy-chain, the following points must be considered:
All devices must share a common ground, connected to GND on the AVR ONE! probe
All devices must be operating on the same target voltage. VTref on the AVR ONE! probe must be connected to this voltage.
TMS and TCK are connected in parallel; TDI and TDO are connected in a serial chain.
NSRST on the AVR ONE! probe must be connected to RESET on the devices if any one of the devices in the chain disables its JTAG port.
"Devices before" refers to the number of JTAG devices that the TDI signal has to pass through in the daisy chain before reaching the target device. Similarly "devices after" is the number of devices that the signal has to pass through after the target device before reaching the AVR ONE! TDO pin.
"Instruction bits before" and "after" refers to the sum total of all JTAG devices' instruction register lengths which are connected before and after the target device in the daisy chain.
The total IR length (instruction bits before + AVR IR length + instruction bits after) is limited to a maximum of 240 bits.
Daisy chaining example: TDI -> ATmega1280 -> ATxmega128A1 -> ATUC3A0512 -> TDO
In order to connect to the XMEGA device, the daisy chain settings are:
Devices before: 1
Devices after: 1
Instruction bits before: 4 (AVR devices have 4 IR bits)
Instruction bits before: 5 (AVR32 devices have 5 IR bits)
When debugging AVR target devices that feature an auxiliary port, it is recommended to use the 38-pin connector, which provides access to both JTAG and AUX ports. The AUX port facilitates advanced debugging features such as program trace.
The pinout of the 38-pin connector is shown in Figure 4.4, “Mictor Connector Pinout” and listed in Table 4.2, “Mictor Connector Pinout”.
The MICTOR Connector is available from Tyco Electronics (part number 2-5767004-2)
Table 4.2. Mictor Connector Pinout
Name | Pin | Description |
---|---|---|
TCK | 15 | Test Clock |
TMS | 17 | Test Mode Select |
TDI | 19 | Test Data In |
TDO | 11 | Test Data Out |
nTRST | 21 | Test Reset |
nRESET | 9 | Source Reset |
EVTI | 10 | Event In |
EVTO | 32 | Event Out |
MCKO | 34 | Message Clock Out |
MSEO0 | 38 | Message Start/End Out [0] |
MSEO1 | 36 | Message Start/End Out [1] |
MDO0 | 30 | Message Data Out [0] |
MDO1 | 28 | Message Data Out [1] |
MDO2 | 26 | Message Data Out [2] |
MDO3 | 24 | Message Data Out [3] |
MDO4 | 22 | Message Data Out [4] |
MDO5 | 20 | Message Data Out [5] |
VREF | 12 | Target Voltage Reference |
GND | 39-43 | Ground |
The aWire interface makes use the /RESET wire of the AVR device to allow programming and debugging functions. A special enable sequence is transmitted by the AVR ONE! which disables the default /RESET functionality of the pin.
When designing an application PCB which includes an AVR with the aWire interface, it is recommended to use the pinout as shown in Figure 4.5, “aWire header pinout”. The AVR ONE! ships with both 100-mil and 50-mil adapters supporting this pinout.
Tip: since aWire is a half-duplex interface, a pull-up resistor on the /RESET line in the order of 47k is recommended to avoid false start-bit detection when changing direction.
The aWire interface can be used as both a programming and debugging interface, all features of the OCD system available through the 10-pin JTAG interface can also be accessed using aWire.