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00047 #include "compiler.h"
00048 #include "scif_uc3l.h"
00049
00050
00051 #ifdef AVR32_SCIF_102_H_INCLUDED
00052 #undef AVR32_SCIF_DFLL0STEP_MASK
00053 #define AVR32_SCIF_DFLL0STEP_MASK 0x0000001f
00054 #define AVR32_SCIF_DFLL0STEP_MAXSTEP 0
00055 #define AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK 0x0000001f
00056 #define AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET 0
00057 #define AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE 5
00058
00059 #define AVR32_SCIF_MAXSTEP 0
00060 #define AVR32_SCIF_MAXSTEP_MASK 0x0000001f
00061 #define AVR32_SCIF_MAXSTEP_OFFSET 0
00062 #define AVR32_SCIF_MAXSTEP_SIZE 5
00063
00064
00065 #endif
00066
00069
00070
00071 typedef union
00072 {
00073 unsigned long oscctrl0;
00074 avr32_scif_oscctrl0_t OSCCTRL0;
00075 } u_avr32_scif_oscctrl0_t;
00076
00077 typedef union
00078 {
00079 unsigned long oscctrl32;
00080 avr32_scif_oscctrl32_t OSCCTRL32;
00081 } u_avr32_scif_oscctrl32_t;
00082
00083 typedef union
00084 {
00085 unsigned long dfll0conf;
00086 avr32_scif_dfll0conf_t DFLL0CONF;
00087 } u_avr32_scif_dfll0conf_t;
00088
00089 typedef union
00090 {
00091 unsigned long dfll0ssg;
00092 avr32_scif_dfll0ssg_t DFLL0SSG;
00093 } u_avr32_scif_dfll0ssg_t;
00094
00096
00097
00101
00102
00103
00107
00108
00109
00114 long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
00115 {
00116
00117
00118 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00119
00120
00121 #ifdef AVR32SFW_INPUT_CHECK
00122
00123 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00124 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00125 {
00126 return -1;
00127 }
00128
00129 if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00130 && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00131 {
00132 return -1;
00133 }
00134
00135 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00136 {
00137 return -1;
00138 }
00139
00140 if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00141 {
00142 return -1;
00143 }
00144 #endif // AVR32SFW_INPUT_CHECK
00145
00146
00147 u_avr32_scif_oscctrl0.OSCCTRL0.mode = opt->mode;
00148 u_avr32_scif_oscctrl0.OSCCTRL0.gain = opt->gain;
00149 u_avr32_scif_oscctrl0.OSCCTRL0.startup = opt->startup;
00150 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00151 AVR32_ENTER_CRITICAL_REGION( );
00152
00153 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00154
00155 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00156 AVR32_LEAVE_CRITICAL_REGION( );
00157
00158 if(true == wait_for_ready)
00159 {
00160
00161 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00162 return -1;
00163 }
00164
00165 return PASS;
00166 }
00167
00168
00169 bool scif_is_osc_ready(scif_osc_t osc)
00170 {
00171
00172
00173 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00174 }
00175
00176
00177 long int scif_stop_osc(scif_osc_t osc)
00178 {
00179
00180
00181 unsigned long temp = AVR32_SCIF.oscctrl0;
00182 temp &= ~AVR32_SCIF_OSCCTRL0_OSCEN_MASK;
00183
00184 AVR32_ENTER_CRITICAL_REGION( );
00185
00186 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00187
00188 AVR32_SCIF.oscctrl0 = temp;
00189 AVR32_LEAVE_CRITICAL_REGION( );
00190
00191 return PASS;
00192 }
00193
00194
00195 long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal)
00196 {
00197
00198
00199 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00200
00201
00202
00203 u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00204 u_avr32_scif_oscctrl0.OSCCTRL0.gain = (fcrystal < 900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00205 (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00206 (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00207 AVR32_SCIF_OSCCTRL0_GAIN_G3;
00208 AVR32_ENTER_CRITICAL_REGION( );
00209
00210 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00211
00212 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00213 AVR32_LEAVE_CRITICAL_REGION( );
00214
00215
00216 return PASS;
00217 }
00218
00219
00220 long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready)
00221 {
00222
00223
00224 u_avr32_scif_oscctrl0_t u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00225
00226
00227
00228 u_avr32_scif_oscctrl0.OSCCTRL0.startup = startup;
00229 u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00230 AVR32_ENTER_CRITICAL_REGION( );
00231
00232 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00233
00234 AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00235 AVR32_LEAVE_CRITICAL_REGION( );
00236
00237 if(true == wait_for_ready)
00238 {
00239
00240 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00241 return -1;
00242 }
00243
00244 return PASS;
00245 }
00246
00247
00252 long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready)
00253 {
00254 u_avr32_scif_oscctrl32_t u_avr32_scif_oscctrl32 = {AVR32_SCIF.oscctrl32};
00255
00256
00257 #ifdef AVR32SFW_INPUT_CHECK
00258
00259 if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00260 || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00261 {
00262 return -1;
00263 }
00264
00265 if( (opt->mode < SCIF_OSC_MODE_EXT_CLK)
00266 || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL)
00267 || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1)
00268 || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) )
00269 {
00270 return -1;
00271 }
00272
00273 if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00274 {
00275 return -1;
00276 }
00277 #endif // AVR32SFW_INPUT_CHECK
00278
00279 #if (defined(__GNUC__) \
00280 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00281 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00282 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00283
00284
00285
00286 scif_disable_rc32out();
00287 #endif
00288
00289
00290 u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00291 u_avr32_scif_oscctrl32.OSCCTRL32.pinsel = opt->pinsel;
00292 u_avr32_scif_oscctrl32.OSCCTRL32.en32k = opt->en32k;
00293 u_avr32_scif_oscctrl32.OSCCTRL32.en1k = opt->en1k;
00294 u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00295 u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00296 #if (defined(__GNUC__) \
00297 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00298 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00299 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00300
00301 AVR32_ENTER_CRITICAL_REGION( );
00302
00303 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00304 #endif
00305
00306 AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00307 #if (defined(__GNUC__) \
00308 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00309 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00310 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00311
00312 AVR32_LEAVE_CRITICAL_REGION( );
00313 #endif
00314
00315 if(true == wait_for_ready)
00316 {
00317
00318 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00319 return -1;
00320 }
00321
00322 return PASS;
00323 }
00324
00325
00326 long scif_stop_osc32()
00327 {
00328 unsigned long temp = AVR32_SCIF.oscctrl32;
00329 temp &= ~AVR32_SCIF_OSCCTRL32_OSC32EN_MASK;
00330
00331 #if 0
00332 AVR32_ENTER_CRITICAL_REGION( );
00333
00334 SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00335 #endif
00336
00337 AVR32_SCIF.oscctrl32 = temp;
00338 #if 0
00339 AVR32_LEAVE_CRITICAL_REGION( );
00340 #endif
00341
00342 return PASS;
00343 }
00344
00345
00346
00351
00352 typedef enum
00353 {
00354 SCIF_DFLL0_MODE_OPENLOOP = 0,
00355 SCIF_DFLL0_MODE_CLOSEDLOOP
00356 } scif_dfll_mode_t;
00357
00358 long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig)
00359 {
00360 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00361
00362
00363 #ifdef AVR32SFW_INPUT_CHECK
00364 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00365 return -1;
00366 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00367 return -1;
00368 #endif
00369
00370
00371 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00372 AVR32_ENTER_CRITICAL_REGION( );
00373 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00374 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00375 AVR32_LEAVE_CRITICAL_REGION( );
00376
00377
00378 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00379 return -1;
00380
00381
00382 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_OPENLOOP;
00383 AVR32_ENTER_CRITICAL_REGION( );
00384 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00385 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00386 AVR32_LEAVE_CRITICAL_REGION( );
00387
00388
00389 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00390 return -1;
00391
00392
00393 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00394 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00395 AVR32_ENTER_CRITICAL_REGION( );
00396 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00397 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00398 AVR32_LEAVE_CRITICAL_REGION( );
00399
00400
00401 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00402 return -1;
00403
00404 return PASS;
00405 }
00406
00407
00408 #define SCIF_DFLL_COARSE_MAX (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
00409 #define SCIF_DFLL_FINE_MAX (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)
00410 #define SCIF_DFLL_FINE_HALF (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))
00411 long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz)
00412 {
00413 scif_dfll_openloop_conf_t Dfll0Conf;
00414 unsigned long Coarse;
00415 unsigned long Fine;
00416 unsigned long CoarseFreq;
00417 unsigned long DeltaFreq;
00418
00419
00420 #ifdef AVR32SFW_INPUT_CHECK
00421 if((TargetFreqkHz < SCIF_DFLL_MINFREQ_KHZ) || (TargetFreqkHz > SCIF_DFLL_MAXFREQ_KHZ))
00422 return -1;
00423 #endif
00424
00425
00426
00427
00428
00429
00430
00431 Coarse = ((TargetFreqkHz - SCIF_DFLL_MINFREQ_KHZ)*SCIF_DFLL_COARSE_MAX)/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ);
00432
00433 CoarseFreq = SCIF_DFLL_MINFREQ_KHZ + (((SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)/SCIF_DFLL_COARSE_MAX)*Coarse);
00434
00435 DeltaFreq = TargetFreqkHz - CoarseFreq;
00436
00437
00438
00439
00440 Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*2/CoarseFreq*5) + SCIF_DFLL_FINE_HALF;
00441 Fine >>=2;
00442
00443 Dfll0Conf.coarse = Coarse;
00444 Dfll0Conf.fine = Fine;
00445 return(scif_dfll0_openloop_start(&Dfll0Conf));
00446 }
00447
00448 long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig)
00449 {
00450 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00451
00452
00453 #ifdef AVR32SFW_INPUT_CHECK
00454 if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00455 return -1;
00456 #endif
00457
00458
00459
00460
00461 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00462 return -1;
00463
00464
00465 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00466 u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00467 AVR32_ENTER_CRITICAL_REGION( );
00468 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00469 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00470 AVR32_LEAVE_CRITICAL_REGION( );
00471
00472
00473 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00474 return -1;
00475
00476 return PASS;
00477 }
00478
00479
00480 long int scif_dfll0_openloop_stop(void)
00481 {
00482 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00483
00484
00485
00486
00487
00488
00489 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00490 return -1;
00491
00492
00493 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = 0;
00494 AVR32_ENTER_CRITICAL_REGION( );
00495 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00496 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00497 AVR32_LEAVE_CRITICAL_REGION( );
00498
00499
00500 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00501 return -1;
00502
00503
00504 u_avr32_scif_dfll0conf.DFLL0CONF.en = 0;
00505 AVR32_ENTER_CRITICAL_REGION( );
00506 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00507 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00508 AVR32_LEAVE_CRITICAL_REGION( );
00509
00510
00511 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00512 return -1;
00513
00514 return PASS;
00515 }
00516
00517
00518 long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf)
00519 {
00520 u_avr32_scif_dfll0ssg_t u_avr32_scif_dfll0ssg = {AVR32_SCIF.dfll0ssg};
00521
00522
00523 u_avr32_scif_dfll0ssg.DFLL0SSG.en = ENABLE;
00524 u_avr32_scif_dfll0ssg.DFLL0SSG.prbs = pssg_conf->use_random;
00525 u_avr32_scif_dfll0ssg.DFLL0SSG.amplitude = pssg_conf->amplitude;
00526 u_avr32_scif_dfll0ssg.DFLL0SSG.stepsize = pssg_conf->step_size;
00527 AVR32_ENTER_CRITICAL_REGION( );
00528 SCIF_UNLOCK(AVR32_SCIF_DFLL0SSG);
00529 AVR32_SCIF.dfll0ssg = u_avr32_scif_dfll0ssg.dfll0ssg;
00530 AVR32_LEAVE_CRITICAL_REGION( );
00531
00532 return PASS;
00533 }
00534
00535
00536 long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig)
00537 {
00538 u_avr32_scif_dfll0conf_t u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00539
00540
00541 #ifdef AVR32SFW_INPUT_CHECK
00542 if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00543 return -1;
00544 if((pdfllconfig->maxstep >> AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE))
00545 return -1;
00546 #endif
00547
00548
00549 u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00550 AVR32_ENTER_CRITICAL_REGION( );
00551 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00552 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00553 AVR32_LEAVE_CRITICAL_REGION( );
00554
00555
00556 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00557 return -1;
00558
00559
00560 AVR32_ENTER_CRITICAL_REGION( );
00561 SCIF_UNLOCK(AVR32_SCIF_MAXSTEP);
00562 AVR32_SCIF.dfll0step = (pdfllconfig->maxstep << AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK;
00563 AVR32_LEAVE_CRITICAL_REGION( );
00564
00565
00566 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00567 return -1;
00568
00569
00570 AVR32_ENTER_CRITICAL_REGION( );
00571 SCIF_UNLOCK(AVR32_SCIF_DFLL0FMUL);
00572 AVR32_SCIF.dfll0fmul = (pdfllconfig->fmul << AVR32_SCIF_DFLL0FMUL_FMUL_OFFSET)&AVR32_SCIF_DFLL0FMUL_FMUL_MASK;
00573 AVR32_LEAVE_CRITICAL_REGION( );
00574
00575
00576 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00577 return -1;
00578
00579
00580 u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_CLOSEDLOOP;
00581 u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00582 AVR32_ENTER_CRITICAL_REGION( );
00583 SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00584 AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00585 AVR32_LEAVE_CRITICAL_REGION( );
00586
00587
00588 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00589 return -1;
00590
00591
00592
00593 if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0LOCKF_MASK))
00594 return -1;
00595
00596 return PASS;
00597 }
00598
00599
00600 long int scif_dfll0_closedloop_configure_and_start( const scif_gclk_opt_t *gc_dfllif_ref_opt,
00601 unsigned long long target_freq_hz,
00602 bool enable_ssg)
00603 {
00604 scif_dfll_closedloop_conf_t DfllConfig;
00605 int gc_source_clock_freq_hz;
00606
00607
00608
00609
00610 if(SCIF_GCCTRL_SLOWCLOCK == gc_dfllif_ref_opt->clock_source)
00611 gc_source_clock_freq_hz = SCIF_SLOWCLOCK_FREQ_HZ;
00612 else if((SCIF_GCCTRL_OSC32K == gc_dfllif_ref_opt->clock_source) || (SCIF_GCCTRL_RC32K == gc_dfllif_ref_opt->clock_source))
00613 gc_source_clock_freq_hz = SCIF_RC32K_FREQ_HZ;
00614 else if(SCIF_GCCTRL_OSC0 == gc_dfllif_ref_opt->clock_source)
00615 gc_source_clock_freq_hz = gc_dfllif_ref_opt->extosc_f;
00616 else if(SCIF_GCCTRL_RC120M == gc_dfllif_ref_opt->clock_source)
00617 gc_source_clock_freq_hz = SCIF_RC120M_FREQ_HZ;
00618 else if(SCIF_GCCTRL_CLK1K == gc_dfllif_ref_opt->clock_source)
00619 gc_source_clock_freq_hz = 1000;
00620 else
00621 return -1;
00622
00623
00624 if(scif_dfll0_closedloop_mainref_gc_enable(gc_dfllif_ref_opt))
00625 return(-1);
00626
00627
00628
00629 DfllConfig.coarse = ((unsigned long long)(target_freq_hz - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00630
00631
00632
00633 if(0 == gc_dfllif_ref_opt->diven)
00634 DfllConfig.fmul = ((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz;
00635 else
00636 DfllConfig.fmul = ((((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz)<<1)*(1+gc_dfllif_ref_opt->divider);
00637
00638
00639 #if (defined(__GNUC__) \
00640 && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00641 ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00642 && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00643
00644 DfllConfig.maxstep = 0x0040004;
00645 #else
00646
00647
00648
00649
00650
00651
00652 DfllConfig.maxstep = 0x0040004;
00653 #endif
00654
00655
00656
00657
00658
00659
00660
00661
00662 if(scif_dfll0_closedloop_start(&DfllConfig))
00663 return -1;
00664
00665
00666
00667 if(TRUE == enable_ssg)
00668 {
00669 ;
00670 }
00671 return PASS;
00672 }
00673
00688 void scif_start_rc120M(void)
00689 {
00690 AVR32_ENTER_CRITICAL_REGION( );
00691
00692 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00693 AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00694 AVR32_LEAVE_CRITICAL_REGION( );
00695 }
00696
00697 void scif_stop_rc120M(void)
00698 {
00699 unsigned long temp = AVR32_SCIF.rc120mcr;
00700
00701 temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00702 AVR32_ENTER_CRITICAL_REGION( );
00703
00704 SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00705 AVR32_SCIF.rc120mcr = temp;
00706 AVR32_LEAVE_CRITICAL_REGION( );
00707 }
00708
00709
00710
00714 void scif_start_rc32k(void)
00715 {
00716 AVR32_ENTER_CRITICAL_REGION( );
00717
00718 SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00719 AVR32_SCIF.rc32kcr = AVR32_SCIF_RC32KCR_EN_MASK;
00720 AVR32_LEAVE_CRITICAL_REGION( );
00721 }
00722
00723 void scif_stop_rc32k(void)
00724 {
00725 unsigned long temp = AVR32_SCIF.rc32kcr;
00726
00727 temp &= ~AVR32_SCIF_RC32KCR_EN_MASK;
00728 AVR32_ENTER_CRITICAL_REGION( );
00729
00730 SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00731 AVR32_SCIF.rc32kcr = temp;
00732 AVR32_LEAVE_CRITICAL_REGION( );
00733 }
00734
00735 void scif_disable_rc32out(void)
00736 {
00737 unsigned long temp;
00738 AVR32_ENTER_CRITICAL_REGION( );
00739 temp = AVR32_PM.ppcr & (~AVR32_PM_PPCR_FRC32_MASK);
00740
00741 AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
00742 AVR32_PM.ppcr = temp;
00743 AVR32_LEAVE_CRITICAL_REGION( );
00744 }
00745
00750 long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt)
00751 {
00752 #ifdef AVR32SFW_INPUT_CHECK
00753
00754 if( gclk > AVR32_SCIF_GCLK_NUM )
00755 {
00756 return -1;
00757 }
00758
00759 if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00760 {
00761 return -1;
00762 }
00763 #endif // AVR32SFW_INPUT_CHECK
00764
00765
00766 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00767 return -1;
00768
00769
00770 AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00771 |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00772 |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00773 |(AVR32_SCIF_GCCTRL_CEN_MASK);
00774
00775 return PASS;
00776 }
00777
00778
00779 long int scif_stop_gclk(unsigned int gclk)
00780 {
00781 unsigned int timeout = SCIF_POLL_TIMEOUT;
00782
00783 #ifdef AVR32SFW_INPUT_CHECK
00784
00785 if( gclk > AVR32_SCIF_GCLK_NUM )
00786 {
00787 return -1;
00788 }
00789 #endif // AVR32SFW_INPUT_CHECK
00790
00791
00792 AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00793
00794
00795 while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00796 {
00797 if(--timeout == 0)
00798 return -1;
00799 }
00800
00801 return PASS;
00802 }
00803
00804
00805 long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
00806 {
00807 int restart_gc = false;
00808
00809
00810
00811 divfactor = (divfactor>>1) -1;
00812
00813 #ifdef AVR32SFW_INPUT_CHECK
00814
00815 if( gclk > AVR32_SCIF_GCLK_NUM )
00816 {
00817 return -1;
00818 }
00819
00820 if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00821 {
00822 return -1;
00823 }
00824
00825 if(diven)
00826 {
00827 if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00828 return -1;
00829 }
00830 #endif // AVR32SFW_INPUT_CHECK
00831
00832
00833 if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00834 {
00835 restart_gc = true;
00836 if(scif_stop_gclk(gclk) < 0)
00837 return -1;
00838 }
00839
00840
00841 AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00842 |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00843 |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00844
00845
00846 if(true == restart_gc)
00847 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00848
00849 return PASS;
00850 }
00851
00852
00853 long int scif_gc_enable(unsigned int gclk)
00854 {
00855 #ifdef AVR32SFW_INPUT_CHECK
00856
00857 if( gclk > AVR32_SCIF_GCLK_NUM )
00858 {
00859 return -1;
00860 }
00861 #endif // AVR32SFW_INPUT_CHECK
00862
00863
00864 if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00865 AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00866
00867 return PASS;
00868 }
00869
00887 long int scif_pclksr_statushigh_wait(unsigned long statusMask)
00888 {
00889 unsigned int timeout = SCIF_POLL_TIMEOUT;
00890
00891 while(!(AVR32_SCIF.pclksr & statusMask))
00892 {
00893 if(--timeout == 0)
00894 return -1;
00895 }
00896 return PASS;
00897 }