Definition in file power_clocks_lib.h.
#include <avr32/io.h>
#include "compiler.h"
#include "pm.h"
Go to the source code of this file.
Clocks Management | |
#define | pcl_disable_module(module) pm_disable_module(&AVR32_PM, module) |
Disable the clock of a module. | |
#define | pcl_enable_module(module) pm_enable_module(&AVR32_PM, module) |
Enable the clock of a module. | |
#define | pcl_freq_param_t pm_freq_param_t |
Input and output parameters to configure clocks with pcl_configure_clocks(). | |
#define | PCL_NOT_SUPPORTED (-10000) |
Define "not supported" for the lib. | |
enum | pcl_dfll_t { PCL_DFLL0 = 0, PCL_DFLL1 = 1 } |
The different DFLLs. More... | |
enum | pcl_mainclk_t { PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_OSC1, PCL_MC_OSC0_PLL0, PCL_MC_OSC1_PLL0, PCL_MC_OSC0_PLL1, PCL_MC_OSC1_PLL1, PCL_MC_DFLL0, PCL_MC_DFLL1, PCL_MC_RC120M, PCL_MC_RC8M, PCL_MC_CRIPOSC } |
Possible Main Clock Sources. More... | |
enum | pcl_osc_t { PCL_OSC0 = 0, PCL_OSC1 = 1 } |
The different oscillators. More... | |
long int | pcl_configure_clocks (pcl_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks. | |
long int | pcl_configure_clocks_dfll0 (pcl_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock. | |
long int | pcl_configure_clocks_osc0 (pcl_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock. | |
long int | pcl_configure_clocks_rc120m (pcl_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock. | |
long int | pcl_configure_clocks_rcsys (pcl_freq_param_t *param) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock. | |
long int | pcl_configure_usb_clock (void) |
Configure the USB Clock. | |
long int | pcl_switch_to_osc (pcl_osc_t osc, unsigned int fcrystal, unsigned int startup) |
Switch the main clock source to Osc0 configured in crystal mode. | |
Functions | |
Power Management | |
unsigned long | pcl_read_gplp (unsigned long gplp) |
Read the content of the GPLP registers. | |
void | pcl_write_gplp (unsigned long gplp, unsigned long value) |
Write into the GPLP registers. |
#define pcl_disable_module | ( | module | ) | pm_disable_module(&AVR32_PM, module) |
Disable the clock of a module.
module | The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section). |
0 | Success. | |
<0 | An error occured. |
Definition at line 337 of file power_clocks_lib.h.
#define pcl_enable_module | ( | module | ) | pm_enable_module(&AVR32_PM, module) |
Enable the clock of a module.
module | The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section). |
0 | Success. | |
<0 | An error occured. |
Definition at line 318 of file power_clocks_lib.h.
#define pcl_freq_param_t pm_freq_param_t |
Input and output parameters to configure clocks with pcl_configure_clocks().
Definition at line 116 of file power_clocks_lib.h.
#define PCL_NOT_SUPPORTED (-10000) |
Define "not supported" for the lib.
Definition at line 153 of file power_clocks_lib.h.
Referenced by pcl_configure_usb_clock(), and pcl_switch_to_osc().
enum pcl_dfll_t |
The different DFLLs.
Definition at line 89 of file power_clocks_lib.h.
00090 { 00091 PCL_DFLL0 = 0, 00092 PCL_DFLL1 = 1 00093 } pcl_dfll_t;
enum pcl_mainclk_t |
Possible Main Clock Sources.
PCL_MC_RCSYS | |
PCL_MC_OSC0 | |
PCL_MC_OSC1 | |
PCL_MC_OSC0_PLL0 | |
PCL_MC_OSC1_PLL0 | |
PCL_MC_OSC0_PLL1 | |
PCL_MC_OSC1_PLL1 | |
PCL_MC_DFLL0 | |
PCL_MC_DFLL1 | |
PCL_MC_RC120M | |
PCL_MC_RC8M | |
PCL_MC_CRIPOSC |
Definition at line 96 of file power_clocks_lib.h.
00097 { 00098 PCL_MC_RCSYS, // Default main clock source, supported by all (aka Slow Clock) 00099 PCL_MC_OSC0, // Supported by all 00100 PCL_MC_OSC1, // Supported by UC3C only 00101 PCL_MC_OSC0_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference) 00102 PCL_MC_OSC1_PLL0, // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference) 00103 PCL_MC_OSC0_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC0 as reference) 00104 PCL_MC_OSC1_PLL1, // Supported by UC3C (the main clock source is PLL1 with OSC1 as reference) 00105 PCL_MC_DFLL0, // Supported by UC3L 00106 PCL_MC_DFLL1, // Not supported yet 00107 PCL_MC_RC120M, // Supported by UC3L, UC3C 00108 PCL_MC_RC8M, // Supported by UC3C 00109 PCL_MC_CRIPOSC // Supported by UC3C 00110 } pcl_mainclk_t;
enum pcl_osc_t |
long int pcl_configure_clocks | ( | pcl_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks.
This function needs some parameters stored in a pcl_freq_param_t structure:
The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.
param | pointer on the configuration structure. |
0 | Success. | |
<0 | The configuration cannot be performed. |
Definition at line 62 of file power_clocks_lib.c.
References pcl_configure_clocks_uc3l(), and pm_configure_clocks().
00063 { 00064 #ifndef AVR32_PM_VERSION_RESETVALUE 00065 // Implementation for UC3A, UC3A3, UC3B parts. 00066 return(pm_configure_clocks(param)); 00067 #else 00068 #ifdef AVR32_PM_410_H_INCLUDED 00069 // Implementation for UC3C parts. 00070 return(pcl_configure_clocks_uc3c(param)); 00071 #else 00072 // Implementation for UC3L parts. 00073 return(pcl_configure_clocks_uc3l(param)); 00074 #endif 00075 #endif 00076 }
long int pcl_configure_clocks_dfll0 | ( | pcl_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.
This function needs some parameters stored in a pcl_freq_param_t structure:
Supported synchronous clocks frequencies: (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_dfll0() and modify it to use preprocessor computation from pre-defined target frequencies.
param | pointer on the configuration structure. |
0 | Success. | |
<0 | The configuration cannot be performed. |
Definition at line 180 of file power_clocks_lib.c.
References pcl_configure_synchronous_clocks(), and PM_CLK_SRC_DFLL0.
Referenced by pcl_configure_clocks_uc3l().
00181 { 00182 // Supported main clock sources: PCL_MC_DFLL 00183 00184 // Supported synchronous clocks frequencies if DFLL is the main clock source: 00185 // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) 00186 // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz. 00187 00188 // NOTE: by default, this implementation doesn't perform thorough checks on the 00189 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. 00190 00191 unsigned long main_clock_freq; 00192 scif_gclk_opt_t *pgc_dfllif_ref_opt; 00193 00194 00195 #ifdef AVR32SFW_INPUT_CHECK 00196 // Verify that fCPU >= fPBx 00197 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) 00198 return(-1); 00199 #endif 00200 00201 main_clock_freq = param->dfll_f; 00202 #ifdef AVR32SFW_INPUT_CHECK 00203 // Verify that the target DFLL output frequency is in the correct range. 00204 if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ)) 00205 return(-1); 00206 // Verify that the target frequencies are reachable. 00207 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) 00208 || (param->pbb_f > main_clock_freq)) 00209 return(-1); 00210 #endif 00211 pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params; 00212 // Implementation note: this implementation configures the DFLL in closed-loop 00213 // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF 00214 // as a reference (RCSYS being used as the generic clock source, undivided). 00215 scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE); 00216 00217 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param)); 00218 }
long int pcl_configure_clocks_osc0 | ( | pcl_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.
This function needs some parameters stored in a pcl_freq_param_t structure:
Supported main clock sources: PCL_MC_OSC0
Supported synchronous clocks frequencies: (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_osc0() and modify it to use preprocessor computation from pre-defined target frequencies.
param | pointer on the configuration structure. |
0 | Success. | |
<0 | The configuration cannot be performed. |
Definition at line 144 of file power_clocks_lib.c.
References pcl_configure_synchronous_clocks(), and PM_CLK_SRC_OSC0.
Referenced by pcl_configure_clocks_uc3l().
00145 { 00146 // Supported main clock sources: PCL_MC_OSC0 00147 00148 // Supported synchronous clocks frequencies if OSC0 is the main clock source: 00149 // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) 00150 // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz. 00151 00152 // NOTE: by default, this implementation doesn't perform thorough checks on the 00153 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. 00154 00155 unsigned long main_clock_freq; 00156 00157 00158 #ifdef AVR32SFW_INPUT_CHECK 00159 // Verify that fCPU >= fPBx 00160 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) 00161 return(-1); 00162 #endif 00163 00164 main_clock_freq = param->osc0_f; 00165 #ifdef AVR32SFW_INPUT_CHECK 00166 // Verify that the target frequencies are reachable. 00167 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq) 00168 || (param->pbb_f > main_clock_freq)) 00169 return(-1); 00170 #endif 00171 // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. 00172 scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq); 00173 // Enable the OSC0 00174 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); 00175 00176 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param)); 00177 }
long int pcl_configure_clocks_rc120m | ( | pcl_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
This function needs some parameters stored in a pcl_freq_param_t structure:
Supported main clock sources: PCL_MC_RC120M
Supported synchronous clocks frequencies: 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rc120m() and modify it to use preprocessor computation from pre-defined target frequencies.
param | pointer on the configuration structure. |
0 | Success. | |
<0 | The configuration cannot be performed. |
Definition at line 114 of file power_clocks_lib.c.
References pcl_configure_synchronous_clocks(), and PM_CLK_SRC_RC120M.
Referenced by pcl_configure_clocks_uc3l().
00115 { 00116 // Supported main clock sources: PCL_MC_RC120M 00117 00118 // Supported synchronous clocks frequencies if RC120M is the main clock source: 00119 // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz. 00120 00121 // NOTE: by default, this implementation doesn't perform thorough checks on the 00122 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. 00123 00124 #ifdef AVR32SFW_INPUT_CHECK 00125 // Verify that fCPU >= fPBx 00126 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) 00127 return(-1); 00128 #endif 00129 00130 #ifdef AVR32SFW_INPUT_CHECK 00131 // Verify that the target frequencies are reachable. 00132 if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ) 00133 || (param->pbb_f > SCIF_RC120M_FREQ_HZ)) 00134 return(-1); 00135 #endif 00136 00137 // Start the 120MHz internal RCosc (RC120M) clock 00138 scif_start_rc120M(); 00139 00140 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param)); 00141 }
long int pcl_configure_clocks_rcsys | ( | pcl_freq_param_t * | param | ) |
Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
This function needs some parameters stored in a pcl_freq_param_t structure:
Supported main clock sources: PCL_MC_RCSYS
Supported synchronous clocks frequencies: 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rcsys() and modify it to use preprocessor computation from pre-defined target frequencies.
param | pointer on the configuration structure. |
0 | Success. | |
<0 | The configuration cannot be performed. |
Definition at line 87 of file power_clocks_lib.c.
References pcl_configure_synchronous_clocks(), and PM_CLK_SRC_SLOW.
Referenced by pcl_configure_clocks_uc3l().
00088 { 00089 // Supported main clock sources: PCL_MC_RCSYS 00090 00091 // Supported synchronous clocks frequencies if RCSYS is the main clock source: 00092 // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz. 00093 00094 // NOTE: by default, this implementation doesn't perform thorough checks on the 00095 // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK. 00096 00097 #ifdef AVR32SFW_INPUT_CHECK 00098 // Verify that fCPU >= fPBx 00099 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f)) 00100 return(-1); 00101 #endif 00102 00103 #ifdef AVR32SFW_INPUT_CHECK 00104 // Verify that the target frequencies are reachable. 00105 if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ) 00106 || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ)) 00107 return(-1); 00108 #endif 00109 00110 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param)); 00111 }
long int pcl_configure_usb_clock | ( | void | ) |
Configure the USB Clock.
0 | Success. | |
<0 | An error occured. |
Definition at line 508 of file power_clocks_lib.c.
References PCL_NOT_SUPPORTED, and pm_configure_usb_clock().
00509 { 00510 #ifndef AVR32_PM_VERSION_RESETVALUE 00511 // Implementation for UC3A, UC3A3, UC3B parts. 00512 pm_configure_usb_clock(); 00513 #else 00514 #ifdef AVR32_PM_410_H_INCLUDED 00515 const scif_pll_opt_t opt = { 00516 .osc = SCIF_OSC0, // Sel Osc0 or Osc1 00517 .lockcount = 16, // lockcount in main clock for the PLL wait lock 00518 .div = 1, // DIV=1 in the formula 00519 .mul = 5, // MUL=7 in the formula 00520 .pll_div2 = 1, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) 00521 .pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. 00522 .pll_freq = 1, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. 00523 }; 00524 00525 /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */ 00526 scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock 00527 00528 /* Enable PLL1 */ 00529 scif_pll_enable(SCIF_PLL1); 00530 00531 /* Wait for PLL1 locked */ 00532 scif_wait_for_pll_locked(SCIF_PLL1) ; 00533 00534 // Implementation for UC3C parts. 00535 // Setup the generic clock for USB 00536 scif_gc_setup(AVR32_SCIF_GCLK_USB, 00537 SCIF_GCCTRL_PLL1, 00538 AVR32_SCIF_GC_NO_DIV_CLOCK, 00539 0); 00540 // Now enable the generic clock 00541 scif_gc_enable(AVR32_SCIF_GCLK_USB); 00542 #else 00543 return PCL_NOT_SUPPORTED; 00544 #endif 00545 #endif 00546 return PASS; 00547 }
unsigned long pcl_read_gplp | ( | unsigned long | gplp | ) |
Read the content of the GPLP registers.
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) |
long int pcl_switch_to_osc | ( | pcl_osc_t | osc, | |
unsigned int | fcrystal, | |||
unsigned int | startup | |||
) |
Switch the main clock source to Osc0 configured in crystal mode.
osc | The oscillator to enable and switch to. | |
fcrystal | Oscillator external crystal frequency (Hz) | |
startup | Oscillator startup time. |
0 | Success. | |
<0 | An error occured. |
Definition at line 463 of file power_clocks_lib.c.
References PCL_NOT_SUPPORTED, PCL_OSC0, PM_CLK_SRC_OSC0, pm_set_mclk_source(), and pm_switch_to_osc0().
00464 { 00465 #ifndef AVR32_PM_VERSION_RESETVALUE 00466 // Implementation for UC3A, UC3A3, UC3B parts. 00467 if(PCL_OSC0 == osc) 00468 { 00469 // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency, 00470 // enable the OSC0, set the main clock source as being OSC0. 00471 pm_switch_to_osc0(&AVR32_PM, fcrystal, startup); 00472 } 00473 else 00474 { 00475 return PCL_NOT_SUPPORTED; 00476 } 00477 #else 00478 // Implementation for UC3C, UC3L parts. 00479 #if AVR32_PM_VERSION_RESETVALUE < 0x400 00480 return PCL_NOT_SUPPORTED; 00481 #else 00482 if(PCL_OSC0 == osc) 00483 { 00484 // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency. 00485 scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal); 00486 // Enable the OSC0 00487 scif_enable_osc(SCIF_OSC0, startup, true); 00488 // Set the Flash wait state and the speed read mode (depending on the target CPU frequency). 00489 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \ 00490 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) ))) 00491 flashcdw_set_flash_waitstate_and_readmode(fcrystal); 00492 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \ 00493 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__))) 00494 flashc_set_flash_waitstate_and_readmode(fcrystal); 00495 #endif 00496 // Set the main clock source as being OSC0. 00497 pm_set_mclk_source(PM_CLK_SRC_OSC0); 00498 } 00499 else 00500 { 00501 return PCL_NOT_SUPPORTED; 00502 } 00503 #endif 00504 #endif 00505 return PASS; 00506 }
void pcl_write_gplp | ( | unsigned long | gplp, | |
unsigned long | value | |||
) |
Write into the GPLP registers.
gplp | GPLP register index (0,1,... depending on the number of GPLP registers for a given part) | |
value | Value to write |