pm_example2.c File Reference


Detailed Description

High frequency Main clock source and Generic clock configurations.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm_example2.c.

#include "board.h"
#include "gpio.h"
#include "scif_uc3l.h"
#include "pm_uc3l.h"
#include "flashcdw.h"

Go to the source code of this file.

Defines

Generic Clock Configuration
#define EXAMPLE_CPUCLK_HZ   (48000000UL)
#define EXAMPLE_DFLL_COARSE_FDFLL96   150
#define EXAMPLE_DFLL_FINE_FDFLL96   65
#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION
#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG
#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Functions

static void local_start_gc (void)
static void local_start_highfreq_clock (void)
int main (void)
static void software_delay (void)


Define Documentation

#define EXAMPLE_CPUCLK_HZ   (48000000UL)

Definition at line 153 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_DFLL_COARSE_FDFLL96   150

Definition at line 156 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_DFLL_FINE_FDFLL96   65

Definition at line 157 of file pm_example2.c.

Referenced by local_start_highfreq_clock().

#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION

Definition at line 152 of file pm_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG

Definition at line 150 of file pm_example2.c.

Referenced by local_start_gc().

#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Definition at line 151 of file pm_example2.c.

Referenced by local_start_gc().


Function Documentation

static void local_start_gc ( void   )  [static]

Definition at line 310 of file pm_example2.c.

References EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, pm_gc_enable(), and pm_gc_setup().

Referenced by main().

00311 {
00312 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
00313   // Note: for UC3L devices, the generic clock configurations are handled by the
00314   // SCIF module.
00315   // Setup gc to use the DFLL0 as source clock, divisor enabled, apply a division factor.
00316   // Since the DFLL0 frequency is 96MHz, set the division factor to 2 to have a
00317   // gclk frequency of 48MHz.
00318   scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 2);
00319 
00320   /* Now enable the generic clock */
00321   scif_gc_enable(EXAMPLE_GCLK_ID);
00322 #elif BOARD == UC3C_EK 
00323   // Note: for UC3L and UC3C devices, the generic clock configurations are handled by the
00324   // SCIF module.
00325   /* setup gc on Osc0, no divisor */
00326   scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_PLL0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
00327   
00328   /* Now enable the generic clock */
00329   scif_gc_enable(EXAMPLE_GCLK_ID);
00330 #else
00331   volatile avr32_pm_t* pm = &AVR32_PM;
00332   /* Setup generic clock on PLL0, with Osc0/PLL0, no divisor */
00333   /*
00334   void pm_gc_setup(volatile avr32_pm_t* pm,
00335                   unsigned int gc,
00336                   unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
00337                   unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
00338                   unsigned int diven,
00339                   unsigned int div) {
00340   */
00341   pm_gc_setup(pm,
00342               EXAMPLE_GCLK_ID,
00343               1,  // Use Osc (=0) or PLL (=1), here PLL
00344               0,  // Sel Osc0/PLL0 or Osc1/PLL1
00345               0,  // disable divisor
00346               0); // no divisor
00347 
00348   /* Enable Generic clock */
00349   pm_gc_enable(pm, EXAMPLE_GCLK_ID);
00350 #endif
00351   /* Set the GCLOCK function to the GPIO pin */
00352   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00353 }

static void local_start_highfreq_clock ( void   )  [static]

Definition at line 177 of file pm_example2.c.

References EXAMPLE_CPUCLK_HZ, EXAMPLE_DFLL_COARSE_FDFLL96, EXAMPLE_DFLL_FINE_FDFLL96, flashc_set_wait_state(), pm_cksel(), PM_CKSEL_DIVRATIO_2, PM_CKSEL_DIVRATIO_4, PM_CLK_DOMAIN_2, PM_CLK_SRC_DFLL0, PM_CLK_SRC_OSC0, pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), pm_set_clk_domain_div(), pm_set_mclk_source(), pm_switch_to_clock(), pm_switch_to_osc0(), and pm_wait_for_pll0_locked().

Referenced by main().

00178 {
00179 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK
00180   scif_dfll_openloop_conf_t dfllconfig = {EXAMPLE_DFLL_FINE_FDFLL96, EXAMPLE_DFLL_COARSE_FDFLL96};
00181 
00182   // Configure and start the DFLL0 in open loop mode to generate a frequency of 96MHz.
00183   scif_dfll0_openloop_start(&dfllconfig);
00184   
00185   // Since our target is to set the CPU&HSB frequency domains to 48MHz, we must
00186   // set one wait-state and enable the High-speed read mode on the flash controller. 
00187   flashcdw_set_flash_waitstate_and_readmode(EXAMPLE_CPUCLK_HZ);
00188   
00189   // Set the CPU clock domain to 48MHz (by applying a division ratio = 2).
00190   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, PM_CKSEL_DIVRATIO_2);
00191   
00192   // Set the PBA clock domain to 24MHz (by applying a division ratio = 4).
00193   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_4);
00194   
00195   // Set the PBB clock domain to 48MHz (by applying a division ratio = 2).
00196   pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, PM_CKSEL_DIVRATIO_2);
00197   
00198   // Set the main clock source to be DFLL0.
00199   pm_set_mclk_source(PM_CLK_SRC_DFLL0);
00200 #elif BOARD == UC3C_EK
00201   
00202   scif_pll_opt_t opt;
00203   
00204   // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00205   scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00206   
00207   // Enable the OSC0
00208   scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00209   
00210   // Set the main clock source as being OSC0.
00211   pm_set_mclk_source(PM_CLK_SRC_OSC0);
00212 
00213   opt.osc = SCIF_OSC0;     // Sel Osc0 or Osc1
00214   opt.lockcount = 16;      // lockcount in main clock for the PLL wait lock
00215   opt.div = 1;             // DIV=1 in the formula
00216   opt.mul = 5;             // MUL=6 in the formula
00217   opt.pll_div2 = 1;        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00218   opt.pll_wbwdisable = 0;  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00219   opt.pll_freq = 1;        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00220 
00221   scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
00222       
00223   /* Enable PLL0 */
00224   scif_pll_enable(SCIF_PLL0);
00225 
00226   /* Wait for PLL0 locked */
00227   scif_wait_for_pll_locked(SCIF_PLL0) ;
00228   
00229   /* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
00230      Pheripheral Bus A clock divisor enable = 1
00231      Pheripheral Bus A select = 0
00232      Pheripheral Bus B clock divisor enable = 0
00233      Pheripheral Bus B select = 0
00234      High Speed Bus clock divisor enable = 0
00235      High Speed Bus select = 0
00236   */  
00237   pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
00238 
00239   // Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
00240   // As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
00241   flashc_set_wait_state(1);
00242   
00243   // Set the main clock source as being PLL0.
00244   pm_set_mclk_source(PM_CLK_SRC_PLL0);
00245   
00246 #else
00247   volatile avr32_pm_t* pm = &AVR32_PM;
00248   /* \note All calculations here suppose that the Osc0 frequency is 12MHz. */
00249 
00250   pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP);  // Switch main clock to Osc0.
00251 
00252   /* Setup PLL0 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 12Mhzx8 = 96MHz output */
00253   /*void pm_pll_setup(volatile avr32_pm_t* pm,
00254                   unsigned int pll,
00255                   unsigned int mul,
00256                   unsigned int div,
00257                   unsigned int osc,
00258                   unsigned int lockcount) {
00259    */
00260   pm_pll_setup(pm,
00261                0,   // use PLL0
00262                7,   // MUL=7 in the formula
00263                1,   // DIV=1 in the formula
00264                0,   // Sel Osc0/PLL0 or Osc1/PLL1
00265                16); // lockcount in main clock for the PLL wait lock
00266 
00267   /*
00268    This function will set a PLL option.
00269    *pm Base address of the Power Manager (i.e. &AVR32_PM)
00270    pll PLL number 0
00271    pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00272    pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00273    pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00274   */
00275   /* PLL output VCO frequency is 96MHz. We divide it by 2 with the pll_div2=1. This enable to get later main clock to 48MHz */
00276   pm_pll_set_option(pm, 0, 1, 1, 0);
00277 
00278   /* Enable PLL0 */
00279   /*
00280     void pm_pll_enable(volatile avr32_pm_t* pm,
00281                   unsigned int pll) {
00282   */
00283   pm_pll_enable(pm,0);
00284 
00285   /* Wait for PLL0 locked */
00286   pm_wait_for_pll0_locked(pm) ;
00287 
00288   /* Divide PBA clock by 2 from main clock (PBA clock = 48MHz/2 = 24MHz).
00289      Pheripheral Bus A clock divisor enable = 1
00290      Pheripheral Bus A select = 0
00291      Pheripheral Bus B clock divisor enable = 0
00292      Pheripheral Bus B select = 0
00293      High Speed Bus clock divisor enable = 0
00294      High Speed Bus select = 0
00295   */
00296   pm_cksel(pm, 1, 0, 0, 0, 0, 0);
00297 
00298   // Set one wait-state (WS) for flash controller. 0 WS access is up to 30MHz for HSB/CPU clock.
00299   // As we want to have 48MHz on HSB/CPU clock, we need to set 1 WS on flash controller.
00300   flashc_set_wait_state(1);
00301 
00302   pm_switch_to_clock(pm, AVR32_PM_MCSEL_PLL0); /* Switch main clock to 48MHz */
00303 #endif
00304 }

int main ( void   ) 

Definition at line 373 of file pm_example2.c.

References local_start_gc(), local_start_highfreq_clock(), and software_delay().

00374 {
00375   /* Start a high frequency clock and switch the main clock to that high frequency clock */
00376   local_start_highfreq_clock();
00377   
00378   /* Set-up a generic clock from a high frequency clock and output it to a gpio pin. */
00379   local_start_gc();
00380 
00381   /* Now toggle LED0 using a GPIO */
00382   while(1)
00383   {
00384     gpio_tgl_gpio_pin(LED0_GPIO);
00385     software_delay();
00386   }
00387 }

static void software_delay ( void   )  [static]

Definition at line 358 of file pm_example2.c.

Referenced by main().

00359 {
00360   volatile int i;
00361   for (i=0; i<1000000; i++);
00362 }


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