isp.c File Reference


Detailed Description

Main file of the USB DFU ISP.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file isp.c.

#include "preprocessor.h"
#include "compiler.h"
#include "board.h"
#include "pm.h"
#include "rtc.h"
#include "cycle_counter.h"
#include "flashc.h"
#include "conf_usb.h"
#include "usb_drv.h"
#include "usb_task.h"
#include "usb_dfu.h"
#include "conf_isp.h"
#include "isp.h"
#include "autobaud.h"

Go to the source code of this file.

Defines

#define MAX_OSC_FREQ   16000000
#define PM   (&AVR32_PM)
#define TC   (&AVR32_TC)
#define TC_32KHZ_CHANNEL   0

Functions

int main (void)
static void osc_isp_counter_reset (void)
static int osc_isp_counter_value (void)
static void osc_rtc_counter_reset (void)
static int osc_rtc_counter_value (void)
void sys_clk_gen_start (void)
void sys_clk_gen_stop (void)
void wait_10_ms (void)


Define Documentation

#define MAX_OSC_FREQ   16000000

Referenced by sys_clk_gen_start().

#define PM   (&AVR32_PM)

Definition at line 111 of file isp.c.

Referenced by sys_clk_gen_start().

#define TC   (&AVR32_TC)

Definition at line 109 of file isp.c.

#define TC_32KHZ_CHANNEL   0

Definition at line 112 of file isp.c.


Function Documentation

int main ( void   ) 

Definition at line 291 of file isp.c.

References usb_dfu_init(), and wait_10_ms().

00292 {
00293   wait_10_ms();
00294 
00295   Usb_force_full_speed_mode();
00296   usb_task_init();
00297 #if USB_DEVICE_FEATURE == ENABLED
00298   usb_dfu_init();
00299 #endif
00300 
00301   while (TRUE)
00302   {
00303     usb_task();
00304   }
00305 }

static void osc_isp_counter_reset ( void   )  [static]

Definition at line 130 of file isp.c.

Referenced by sys_clk_gen_start().

00131 {
00132   Set_sys_count(0);
00133 }

static int osc_isp_counter_value ( void   )  [static]

Definition at line 135 of file isp.c.

Referenced by sys_clk_gen_start().

00136 {
00137   return Get_sys_count();
00138 }

static void osc_rtc_counter_reset ( void   )  [static]

Definition at line 120 of file isp.c.

Referenced by sys_clk_gen_start().

00121 {
00122   rtc_set_value(&AVR32_RTC, 0);
00123 }

static int osc_rtc_counter_value ( void   )  [static]

Definition at line 125 of file isp.c.

Referenced by sys_clk_gen_start().

00126 {
00127   return rtc_get_value(&AVR32_RTC) * 2;
00128 }

void sys_clk_gen_start ( void   ) 

Start the generation of system clocks with USB autobaud

Definition at line 143 of file isp.c.

References ISP_OSC, MAX_OSC_FREQ, osc_isp_counter_reset(), osc_isp_counter_value(), osc_rtc_counter_reset(), osc_rtc_counter_value(), and PM.

00144 {
00145   int cpu_freq_hz, mul;
00146   const int freq_hz[] = { 8000000, 12000000, 16000000 };
00147   const struct autobaud_cfg_osc_cmp_t autobaud_cfg = {
00148     .osc_ref_freq_hz = 115000,
00149     .osc_ref_counter_reset = osc_rtc_counter_reset,
00150     .osc_ref_counter_value = osc_rtc_counter_value,
00151     .osc_target_counter_reset = osc_isp_counter_reset,
00152     .osc_target_counter_value = osc_isp_counter_value,
00153     .convergence_rate = 10000
00154   };
00155   const struct autobaud_matching_freq_t match_freq = {
00156     .freq_hz = freq_hz,
00157     .nb_entries = sizeof(freq_hz)/sizeof(freq_hz[0])
00158   };
00159   Bool sav_glob_int_en;
00160 
00161   #define MAX_OSC_FREQ    16000000
00162   
00163 
00164   // Switch to OSC ISP
00165   // Set max startup time to make sure any crystal will be supported
00166   // We cannot use a TC to measure this OSC frequency because the master clock must be faster than the clock selected by the TC
00167   pm_switch_to_osc0(&AVR32_PM, MAX_OSC_FREQ, ATPASTE3(AVR32_PM_OSCCTRL, ISP_OSC, _STARTUP_16384_RCOSC));
00168   // Intialize the RTC with the internal RC oscillator
00169   // RTC will count at the frequency of 115KHz/2
00170   rtc_init(&AVR32_RTC, RTC_OSC_RC, 0);
00171   rtc_enable(&AVR32_RTC);
00172 
00173   // Calculate the frequency
00174   if (!(cpu_freq_hz = autobaud_detect_osc_cmp(&autobaud_cfg)))
00175     cpu_freq_hz = 12000000;
00176   cpu_freq_hz = autobaud_match_frequency(cpu_freq_hz, &match_freq);
00177 
00178   switch (cpu_freq_hz)
00179   {
00180   case 8000000:
00181     mul = 5;
00182     break;
00183   case 12000000:
00184     mul = 3;
00185     break;
00186   case 16000000:
00187     mul = 2;
00188     break;
00189   default:
00190     mul = 3;
00191   }
00192 
00193   Usb_freeze_clock();
00194 
00195   // Set PLL0 VCO @ 96 MHz
00196   pm_pll_setup(PM, 0,                         // pll
00197                    mul,                       // mul
00198                    0,                         // div
00199                    ISP_OSC,                   // osc
00200                    63);                       // lockcount
00201 
00202   if ((sav_glob_int_en = Is_global_interrupt_enabled())) Disable_global_interrupt();
00203 
00204   // Set PLL0 @ 48 MHz
00205   pm_pll_set_option(PM, 0,  // pll
00206                     1,      // pll_freq
00207                     1,      // pll_div2
00208                     0);     // pll_wbwdisable
00209 
00210   // Enable PLL0
00211   pm_pll_enable(PM, 0);
00212 
00213   // Wait for PLL0 locked with a 10-ms time-out
00214   pm_wait_for_pll0_locked(PM);
00215 
00216   // Setup USB GCLK
00217   pm_gc_setup(PM, AVR32_PM_GCLK_USBB, // gc
00218                       1,              // osc_or_pll: use Osc (if 0) or PLL (if 1)
00219                       0,              // pll_osc: select Osc0/PLL0 or Osc1/PLL1
00220 #if (defined __GNUC__) && ((defined __AVR32_UC3A364__)   ||                    \
00221                            (defined __AVR32_UC3A364S__)  ||                    \
00222                            (defined __AVR32_UC3A3128__)  ||                    \
00223                            (defined __AVR32_UC3A3128S__) ||                    \
00224                            (defined __AVR32_UC3A3256__)  ||                    \
00225                            (defined __AVR32_UC3A3256S__))||                    \
00226 (defined __ICCAVR32__) && ((defined __AT32UC3A364__)     ||                    \
00227                            (defined __AT32UC3A364S__)    ||                    \
00228                            (defined __AT32UC3A3128__)    ||                    \
00229                            (defined __AT32UC3A3128S__)   ||                    \
00230                            (defined __AT32UC3A3256__)    ||                    \
00231                            (defined __AT32UC3A3256S__))
00232                       1,                  // diven
00233                       1);                 // div
00234 #else
00235                       0,                  // diven
00236                       0);                 // div
00237 #endif
00238 
00239   // Enable USB GCLK
00240   pm_gc_enable(PM, AVR32_PM_GCLK_USBB);
00241 
00242   Usb_unfreeze_clock();
00243 
00244   // Use 1 flash wait state
00245   flashc_set_wait_state(1);
00246 
00247   // Switch the main clock to PLL0
00248   pm_switch_to_clock(PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
00249 
00250   // fPBA: 12 MHz
00251   // fPBB: 12 MHz
00252   // fHSB: 12 MHz
00253   pm_cksel(PM, 1,   // pbadiv
00254                1,   // pbasel
00255                1,   // pbbdiv
00256                1,   // pbbsel
00257                1,   // hsbdiv
00258                1);  // hsbsel
00259 
00260   // Use 0 flash wait state
00261   flashc_set_wait_state(0);
00262 
00263   Usb_ack_sof();
00264 
00265   if (sav_glob_int_en) Enable_global_interrupt();
00266 }

void sys_clk_gen_stop ( void   ) 

Stop the generation of system clocks and switch to RCOsc

Definition at line 272 of file isp.c.

References ISP_OSC, pm_disable_clk, pm_enable_clk_no_wait, and pm_enable_osc_ext_clock.

Referenced by usb_dfu_dnload().

00273 {
00274   volatile avr32_pm_t *const pm = &AVR32_PM;
00275 
00276   pm_gc_disable(pm, AVR32_PM_GCLK_USBB);
00277   pm_gc_setup(pm, AVR32_PM_GCLK_USBB, 0, 0, 0, 0);
00278   flashc_set_wait_state(1);
00279   pm_cksel(pm, 0, 0, 0, 0, 0, 0);
00280   pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_SLOW);
00281   flashc_set_wait_state(0);
00282   pm_pll_disable(pm, 0);
00283   pm_pll_set_option(pm, 0, 0, 0, 0);
00284   pm_pll_setup(pm, 0, 0, 0, 0, 0);
00285   pm_enable_clk_no_wait(pm, ATPASTE3(AVR32_PM_OSCCTRL, ISP_OSC, _STARTUP_0_RCOSC));
00286   pm_disable_clk(pm);
00287   pm_enable_osc_ext_clock(pm);
00288 }

void wait_10_ms ( void   ) 

Definition at line 114 of file isp.c.

Referenced by main(), and usb_dfu_dnload().

00115 {
00116   Set_system_register(AVR32_COUNT, 0);
00117   while ((U32)Get_system_register(AVR32_COUNT) < (FRCOSC * 10 + 999) / 1000);
00118 }


Generated on Thu Dec 17 20:03:29 2009 for AVR32 - USB DFU Example: ISP by  doxygen 1.5.5