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00050 #include "compiler.h"
00051 #include "ssc_i2s.h"
00052
00053
00070 static int set_clock_divider(volatile avr32_ssc_t *ssc,
00071 unsigned int bit_rate,
00072 unsigned int pba_hz)
00073 {
00076 ssc->cmr = ((pba_hz + bit_rate) / (2 * bit_rate)) << AVR32_SSC_CMR_DIV_OFFSET;
00077
00078 return SSC_I2S_OK;
00079 }
00080
00081
00082 void ssc_i2s_reset(volatile avr32_ssc_t *ssc)
00083 {
00084
00085 ssc->cr = AVR32_SSC_CR_SWRST_MASK;
00086 }
00087
00088
00089 int ssc_i2s_init(volatile avr32_ssc_t *ssc,
00090 unsigned int sample_frequency,
00091 unsigned int data_bit_res,
00092 unsigned int frame_bit_res,
00093 unsigned char mode,
00094 unsigned int pba_hz)
00095 {
00098
00099 ssc_i2s_reset(ssc);
00100
00101 if (mode == SSC_I2S_MODE_SLAVE_STEREO_OUT)
00102 {
00103 ssc->cmr = AVR32_SSC_CMR_DIV_NOT_ACTIVE << AVR32_SSC_CMR_DIV_OFFSET;
00104
00105 ssc->tcmr = AVR32_SSC_TCMR_CKS_TK_PIN << AVR32_SSC_TCMR_CKS_OFFSET |
00106 AVR32_SSC_TCMR_CKO_INPUT_ONLY << AVR32_SSC_TCMR_CKO_OFFSET |
00107 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00108 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00109 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00110 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00111 0 << AVR32_SSC_TCMR_PERIOD_OFFSET;
00112 #ifdef AVR32_SSC_220_H_INCLUDED
00113 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00114 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00115 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00116 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00117 0 << AVR32_SSC_TFMR_FSLEN_OFFSET |
00118 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET |
00119 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00120 0 << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00121 #else
00122 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00123 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00124 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00125 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00126 0 << AVR32_SSC_TFMR_FSLEN_OFFSET |
00127 AVR32_SSC_TFMR_FSOS_INPUT_ONLY << AVR32_SSC_TFMR_FSOS_OFFSET |
00128 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00129 0 << AVR32_SSC_TFMR_FSEDGE_OFFSET |
00130 0 << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00131 #endif
00132 ssc->cr = AVR32_SSC_CR_TXEN_MASK;
00133 }
00134 else
00135 {
00136 unsigned long txen_mask = 0x00000000,
00137 rxen_mask = 0x00000000;
00138
00139 if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00140 {
00141
00142 set_clock_divider(ssc, 2 * sample_frequency * frame_bit_res, pba_hz);
00143 }
00144
00145
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155
00156 if (mode != SSC_I2S_MODE_RIGHT_IN)
00157 {
00158 if (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK)
00159 {
00160
00161
00162
00163
00164
00165
00166
00167
00168
00169
00170
00171 ssc->tcmr = AVR32_SSC_TCMR_CKS_DIV_CLOCK << AVR32_SSC_TCMR_CKS_OFFSET |
00172 AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET |
00173 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00174 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00175 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00176 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00177 (frame_bit_res - 1) << AVR32_SSC_TCMR_PERIOD_OFFSET;
00178 }
00179 else
00180 {
00181
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191
00192 ssc->tcmr = AVR32_SSC_TCMR_CKS_RK_CLOCK << AVR32_SSC_TCMR_CKS_OFFSET |
00193 AVR32_SSC_TCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_TCMR_CKO_OFFSET |
00194 0 << AVR32_SSC_TCMR_CKI_OFFSET |
00195 AVR32_SSC_TCMR_CKG_NONE << AVR32_SSC_TCMR_CKG_OFFSET |
00196 AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF << AVR32_SSC_TCMR_START_OFFSET |
00197 1 << AVR32_SSC_TCMR_STTDLY_OFFSET |
00198 (frame_bit_res - 1) << AVR32_SSC_TCMR_PERIOD_OFFSET;
00199
00200
00201
00202 ssc->rcmr = (AVR32_SSC_RCMR_CKS_RK_PIN << AVR32_SSC_RCMR_CKS_OFFSET);
00203 }
00204
00205
00206
00207
00208
00209
00210
00211
00212
00213
00214
00215 #ifdef AVR32_SSC_220_H_INCLUDED
00216 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00217 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00218 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00219 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00220 (((frame_bit_res - 1) << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00221 AVR32_SSC_TFMR_FSOS_NEG_PULSE << AVR32_SSC_TFMR_FSOS_OFFSET |
00222 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00223 1 << AVR32_SSC_TFMR_FSEDGE_OFFSET;
00224 #else
00225 ssc->tfmr = (data_bit_res - 1) << AVR32_SSC_TFMR_DATLEN_OFFSET |
00226 0 << AVR32_SSC_TFMR_DATDEF_OFFSET |
00227 1 << AVR32_SSC_TFMR_MSBF_OFFSET |
00228 (1 - 1) << AVR32_SSC_TFMR_DATNB_OFFSET |
00229 (((frame_bit_res - 1) << AVR32_SSC_TFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00230 AVR32_SSC_TFMR_FSOS_NEG_PULSE << AVR32_SSC_TFMR_FSOS_OFFSET |
00231 0 << AVR32_SSC_TFMR_FSDEN_OFFSET |
00232 1 << AVR32_SSC_TFMR_FSEDGE_OFFSET |
00233 ((frame_bit_res - 1) >> AVR32_SSC_TFMR_FSLEN_SIZE) << AVR32_SSC_TFMR_FSLENHI_OFFSET;
00234 #endif
00235 txen_mask = AVR32_SSC_CR_TXEN_MASK;
00236 }
00237
00238
00239 if ( (mode != SSC_I2S_MODE_STEREO_OUT) && (mode != SSC_I2S_MODE_STEREO_OUT_EXT_CLK) )
00240 {
00241 if ( (mode == SSC_I2S_MODE_STEREO_OUT_MONO_IN) || (mode == SSC_I2S_MODE_RIGHT_IN) )
00242 {
00243
00244
00245
00246
00247
00248
00249
00250
00251
00252
00253
00254 ssc->rcmr =
00255 (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_CKS_RK_PIN : AVR32_SSC_RCMR_CKS_TK_CLOCK )
00256 << AVR32_SSC_RCMR_CKS_OFFSET)|
00257 (AVR32_SSC_RCMR_CKO_INPUT_ONLY << AVR32_SSC_RCMR_CKO_OFFSET)|
00258 (1 << AVR32_SSC_RCMR_CKI_OFFSET)|
00259 (AVR32_SSC_RCMR_CKG_NONE << AVR32_SSC_RCMR_CKG_OFFSET)|
00260 (( mode == SSC_I2S_MODE_RIGHT_IN ? AVR32_SSC_RCMR_START_DETECT_RISING_RF : AVR32_SSC_RCMR_START_TRANSMIT_START )
00261 << AVR32_SSC_RCMR_START_OFFSET)|
00262 (1 << AVR32_SSC_RCMR_STTDLY_OFFSET)|
00263 (0 << AVR32_SSC_RCMR_PERIOD_OFFSET);
00264
00265
00266
00267
00268
00269
00270
00271
00272
00273
00274 ssc->rfmr =
00275 ((data_bit_res-1) << AVR32_SSC_RFMR_DATLEN_OFFSET)|
00276 (0 << AVR32_SSC_RFMR_LOOP_OFFSET)|
00277 (1 << AVR32_SSC_RFMR_MSBF_OFFSET)|
00278 (0 << AVR32_SSC_RFMR_DATNB_OFFSET)|
00279 (0 << AVR32_SSC_RFMR_FSLEN_OFFSET)|
00280 (AVR32_SSC_RFMR_FSOS_INPUT_ONLY << AVR32_SSC_RFMR_FSOS_OFFSET)|
00281 (0 << AVR32_SSC_RFMR_FSEDGE_OFFSET);
00282
00283 rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00284 }
00285 else
00286 {
00287 ssc->rcmr = AVR32_SSC_RCMR_CKS_TK_CLOCK << AVR32_SSC_RCMR_CKS_OFFSET |
00288 AVR32_SSC_RCMR_CKO_CONTINOUS_CLOCK_OUTPUT << AVR32_SSC_RCMR_CKO_OFFSET |
00289 0 << AVR32_SSC_RCMR_CKI_OFFSET |
00290 AVR32_SSC_RCMR_CKG_NONE << AVR32_SSC_RCMR_CKG_OFFSET |
00291 AVR32_SSC_RCMR_START_DETECT_ANY_EDGE_RF << AVR32_SSC_RCMR_START_OFFSET |
00292 1 << AVR32_SSC_RCMR_STTDLY_OFFSET |
00293 (frame_bit_res - 1) << AVR32_SSC_RCMR_PERIOD_OFFSET;
00294
00295 #ifdef AVR32_SSC_220_H_INCLUDED
00296 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00297 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00298 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00299 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00300 AVR32_SSC_RFMR_FSOS_NEG_PULSE << AVR32_SSC_RFMR_FSOS_OFFSET |
00301 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET;
00302 #else
00303 ssc->rfmr = (data_bit_res - 1) << AVR32_SSC_RFMR_DATLEN_OFFSET |
00304 1 << AVR32_SSC_RFMR_MSBF_OFFSET |
00305 (1 - 1) << AVR32_SSC_RFMR_DATNB_OFFSET |
00306 (((frame_bit_res - 1) << AVR32_SSC_RFMR_FSLEN_OFFSET) & AVR32_SSC_TFMR_FSLEN_MASK) |
00307 AVR32_SSC_RFMR_FSOS_NEG_PULSE << AVR32_SSC_RFMR_FSOS_OFFSET |
00308 1 << AVR32_SSC_RFMR_FSEDGE_OFFSET |
00309 ((frame_bit_res - 1) >> AVR32_SSC_RFMR_FSLEN_SIZE) << AVR32_SSC_RFMR_FSLENHI_OFFSET;
00310 #endif
00311 rxen_mask = AVR32_SSC_CR_RXEN_MASK;
00312 }
00313
00314 }
00315
00316 ssc->cr = txen_mask | rxen_mask;
00317 }
00318
00319 return SSC_I2S_OK;
00320 }
00321
00322
00323 int ssc_i2s_transfer(volatile avr32_ssc_t *ssc, unsigned int data)
00324 {
00325 unsigned int timeout = SSC_I2S_TIMEOUT_VALUE;
00326
00327 while( ( ssc->sr & (1<<AVR32_SSC_SR_TXRDY_OFFSET) ) == 0 &&
00328 timeout > 0 ) {
00329 timeout--;
00330 }
00331
00332 if( timeout <= 0 ) {
00333 return SSC_I2S_TIMEOUT;
00334 }
00335
00336 ssc->thr = data;
00337
00338 return SSC_I2S_OK;
00339 }
00340
00341
00342 void ssc_i2s_disable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask)
00343 {
00344 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00345
00346 if (global_interrupt_enabled) Disable_global_interrupt();
00347 ssc->idr = int_mask;
00348 ssc->sr;
00349 if (global_interrupt_enabled) Enable_global_interrupt();
00350 }
00351
00352
00353 void ssc_i2s_enable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask)
00354 {
00355 ssc->ier = int_mask;
00356 }
00357
00358
00359 unsigned long ssc_i2s_get_status(volatile avr32_ssc_t *ssc)
00360 {
00361 return ssc->sr;
00362 }