00001 /*This file has been prepared for Doxygen automatic documentation generation.*/ 00084 #include "board.h" 00085 #include "gpio.h" 00086 #include "scif_uc3l.h" 00087 #include "power_clocks_lib.h" 00088 00091 00092 #if BOARD == STK600_RCUC3L0 || BOARD == UC3L_EK 00093 #define EXAMPLE_GCLK_ID AVR32_SCIF_GCLK_DFLL0_SSG // Do not use the AVR32_SCIF_GCLK_DFLL0_REF gc. 00094 #define EXAMPLE_GCLK_PIN AVR32_SCIF_GCLK_1_0_PIN // Mapped on STK600.PORTA.PA6; connector PA6 on AT32UC3L-EK 00095 #define EXAMPLE_GCLK_FUNCTION AVR32_SCIF_GCLK_1_0_FUNCTION 00096 #endif 00097 00098 #if !defined(EXAMPLE_GCLK_ID) || \ 00099 !defined(EXAMPLE_GCLK_PIN) || \ 00100 !defined(EXAMPLE_GCLK_FUNCTION) 00101 # error The generic clock configuration to use in this example is missing. 00102 #endif 00103 00105 #define EXAMPLE_FDFLL_KHZ 22579 00106 #define EXAMPLE_FDFLL_HZ 22579200 00107 00109 #define EXAMPLE_GCLK_FREQ_HZ 44100 00110 00112 00116 static void local_start_dfll_clock() 00117 { 00118 scif_dfll_closedloop_conf_t DfllConfig; 00119 scif_gclk_opt_t GcConf; 00120 00121 00122 // 1) Configure and start the DFLL main reference generic clock: 00123 // use the undivided RCOSC slow clock as source for the generic clock. The 00124 // generic clock frequency will thus be ~115kHz. 00125 GcConf.clock_source = SCIF_GCCTRL_SLOWCLOCK; 00126 GcConf.diven = OFF; 00127 // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock 00128 // (i.e. the generic clock dedicated to be the DFLL main reference clock). 00129 scif_dfll0_closedloop_mainref_gc_enable(&GcConf); 00130 00131 // 2) Configure and start the DFLL. 00132 // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)) 00133 DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ); 00134 // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the 00135 // DFLL main reference generic clock) 00136 DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_SLOWCLOCK_FREQ_HZ; 00137 // The maxstep value 00138 DfllConfig.maxstep = 1; 00139 scif_dfll0_closedloop_start(&DfllConfig); 00140 } 00141 00142 00147 static void local_start_gc() 00148 { 00149 // Setup gc on DFLL; the target frequency is 44kHz => divide the DFLL frequency 00150 // by 512 (== EXAMPLE_FDFLL_HZ / EXAMPLE_GCLK_FREQ_HZ). 00151 scif_gc_setup(EXAMPLE_GCLK_ID, SCIF_GCCTRL_DFLL0, AVR32_GC_DIV_CLOCK, 00152 EXAMPLE_FDFLL_HZ/EXAMPLE_GCLK_FREQ_HZ); 00153 00154 // Now enable the generic clock 00155 scif_gc_enable(EXAMPLE_GCLK_ID); 00156 00157 /* Assign a GPIO to generic clock output */ 00158 gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION); 00159 // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48. 00160 } 00161 00162 00163 00164 /* \brief This is an example that shows how to do the following: 00165 * - generate a high frequency clock (~22MHz) with a DFLL in closed-loop mode 00166 * - set-up a generic clock with a DFLL as a source 00167 * - output the generic clock to GCLK_1_0 00168 * - go into the frozen sleep mode (while still maintaining GCLK output) 00169 * 00170 */ 00171 int main(void) 00172 { 00173 // Generate a high frequency clock (~22MHz) with a DFLL in closed-loop mode 00174 local_start_dfll_clock(); 00175 00176 // Set-up a generic clock from a high frequency clock and output it to a gpio pin. 00177 local_start_gc(); 00178 00179 //*** Sleep mode 00180 // If there is a chance that any PB write operations are incomplete, the CPU 00181 // should perform a read operation from any register on the PB bus before 00182 // executing the sleep instruction. 00183 AVR32_INTC.ipr[0]; // Dummy read 00184 00185 // - Go into a sleep mode (while still maintaining GCLK output) 00186 SLEEP(AVR32_PM_SMODE_FROZEN); 00187 00188 while(1); 00189 } 00190