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00046 #ifndef _SCIF_UC3C_H_
00047 #define _SCIF_UC3C_H_
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053 #include "compiler.h"
00054
00055
00056
00057 #ifdef AVR32_SCIF_101_H_INCLUDED
00058 #define AVR32_SCIF_OSCCTRL0_STARTUP_0_RCOSC 0x00000000
00059 #define AVR32_SCIF_OSCCTRL0_STARTUP_128_RCOSC 0x00000002
00060 #define AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC 0x00000006
00061 #define AVR32_SCIF_OSCCTRL0_STARTUP_2048_RCOSC 0x00000003
00062 #define AVR32_SCIF_OSCCTRL0_STARTUP_4096_RCOSC 0x00000004
00063 #define AVR32_SCIF_OSCCTRL0_STARTUP_64_RCOSC 0x00000001
00064 #define AVR32_SCIF_OSCCTRL0_STARTUP_8192_RCOSC 0x00000005
00065 #define AVR32_SCIF_OSCCTRL1_STARTUP_0_RCOSC 0x00000000
00066 #define AVR32_SCIF_OSCCTRL1_STARTUP_128_RCOSC 0x00000002
00067 #define AVR32_SCIF_OSCCTRL1_STARTUP_16384_RCOSC 0x00000006
00068 #define AVR32_SCIF_OSCCTRL1_STARTUP_2048_RCOSC 0x00000003
00069 #define AVR32_SCIF_OSCCTRL1_STARTUP_4096_RCOSC 0x00000004
00070 #define AVR32_SCIF_OSCCTRL1_STARTUP_64_RCOSC 0x00000001
00071 #define AVR32_SCIF_OSCCTRL1_STARTUP_8192_RCOSC 0x00000005
00072 #define AVR32_SCIF_OSCCTRL32_STARTUP_0_RCOSC 0x00000000
00073 #define AVR32_SCIF_OSCCTRL32_STARTUP_128_RCOSC 0x00000001
00074 #define AVR32_SCIF_OSCCTRL32_STARTUP_131072_RCOSC 0x00000005
00075 #define AVR32_SCIF_OSCCTRL32_STARTUP_16384_RCOSC 0x00000003
00076 #define AVR32_SCIF_OSCCTRL32_STARTUP_262144_RCOSC 0x00000006
00077 #define AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC 0x00000007
00078 #define AVR32_SCIF_OSCCTRL32_STARTUP_65536_RCOSC 0x00000004
00079 #define AVR32_SCIF_OSCCTRL32_STARTUP_8192_RCOSC 0x00000002
00080 #define AVR32_SCIF_OSCCTRL0_MODE_CRYSTAL 0x00000001
00081 #define AVR32_SCIF_OSCCTRL0_MODE_EXTCLK 0x00000000
00082 #define AVR32_SCIF_OSCCTRL0_GAIN_G0 0x00000000
00083 #define AVR32_SCIF_OSCCTRL0_GAIN_G1 0x00000001
00084 #define AVR32_SCIF_OSCCTRL0_GAIN_G2 0x00000002
00085 #define AVR32_SCIF_OSCCTRL0_GAIN_G3 0x00000003
00086 #define AVR32_SCIF_OSCCTRL1_GAIN_G0 0x00000000
00087 #define AVR32_SCIF_OSCCTRL1_GAIN_G1 0x00000001
00088 #define AVR32_SCIF_OSCCTRL1_GAIN_G2 0x00000002
00089 #define AVR32_SCIF_OSCCTRL1_GAIN_G3 0x00000003
00090 #define AVR32_SCIF_UNLOCK_KEY_VALUE 0x000000AA
00091 #define AVR32_SCIF_OSCCTRL_OSCEN_ENABLE 0x00000001
00092 #define AVR32_SCIF_OSCCTRL_OSCEN_DISABLE 0x00000000
00093 #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001
00094 #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000
00095 #endif
00096
00097
00099 #if ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00100 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00101
00102
00104 #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000
00106 #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000
00107
00109 typedef enum
00110 {
00111 SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW,
00112 SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32,
00113 SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0,
00114 SCIF_GCCTRL_OSC1 = AVR32_SCIF_GC_USES_OSC1,
00115 SCIF_GCCTRL_PLL0 = AVR32_SCIF_GC_USES_PLL0,
00116 SCIF_GCCTRL_PLL1 = AVR32_SCIF_GC_USES_PLL1,
00117 SCIF_GCCTRL_RC8M = AVR32_SCIF_GC_USES_RCOSC8,
00118 SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU,
00119 SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB,
00120 SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA,
00121 SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB,
00122 SCIF_GCCTRL_OSCSEL_INVALID
00123 } scif_gcctrl_oscsel_t;
00124
00125 #endif
00126
00127
00129 #define SCIF_POLL_TIMEOUT 100000
00130
00132 #define SCIF_NOT_SUPPORTED (-10000)
00133
00134
00136 typedef enum
00137 {
00138 SCIF_OSC0 = 0,
00139 SCIF_OSC1 = 1
00140 } scif_osc_t;
00141
00143 typedef enum
00144 {
00145 SCIF_PLL0 = 0,
00146 SCIF_PLL1 = 1
00147 } scif_pll_t;
00148
00150 typedef enum
00151 {
00152 SCIF_OSC_MODE_EXT_CLK = 0,
00153 SCIF_OSC_MODE_2PIN_CRYSTAL = 1,
00154 SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 2,
00155 } scif_osc_mode_t;
00156
00158 typedef struct
00159 {
00161 unsigned long freq_hz;
00163 scif_osc_mode_t mode;
00165 unsigned char startup;
00167 unsigned char gain;
00168 } scif_osc_opt_t;
00169
00171 typedef struct
00172 {
00174 unsigned char pll_freq;
00176 unsigned char pll_wbwdisable;
00178 unsigned char pll_div2;
00180 unsigned int mul;
00182 unsigned int div;
00184 unsigned int lockcount;
00186 unsigned char osc;
00187 } scif_pll_opt_t;
00188
00190 typedef struct
00191 {
00193 unsigned long freq_hz;
00195 scif_osc_mode_t mode;
00197 unsigned char startup;
00198 } scif_osc32_opt_t;
00199
00200
00202 typedef struct
00203 {
00205 scif_gcctrl_oscsel_t clock_source;
00207 unsigned int divider;
00209 unsigned int diven;
00210 } scif_gclk_opt_t;
00211
00212
00214 #define SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
00215
00218
00219
00224 #if defined (__GNUC__)
00225 __attribute__((__always_inline__))
00226 #endif
00227 extern __inline__ void scif_enable_interrupts(unsigned long mask)
00228 {
00229 AVR32_SCIF.ier = mask;
00230 }
00231
00236 #if defined (__GNUC__)
00237 __attribute__((__always_inline__))
00238 #endif
00239 extern __inline__ void scif_disable_interrupts(unsigned long mask)
00240 {
00241 AVR32_SCIF.idr = mask;
00242 }
00243
00248 #if defined (__GNUC__)
00249 __attribute__((__always_inline__))
00250 #endif
00251 extern __inline__ unsigned long scif_get_enabled_interrupts(void)
00252 {
00253 return(AVR32_SCIF.imr);
00254 }
00255
00260 #if defined (__GNUC__)
00261 __attribute__((__always_inline__))
00262 #endif
00263 extern __inline__ unsigned long scif_get_interrupts_status(void)
00264 {
00265 return(AVR32_SCIF.isr);
00266 }
00267
00272 #if defined (__GNUC__)
00273 __attribute__((__always_inline__))
00274 #endif
00275 extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
00276 {
00277 AVR32_SCIF.icr = mask;
00278 }
00279
00281
00282
00285
00286
00291 #if defined (__GNUC__)
00292 __attribute__((__always_inline__))
00293 #endif
00294 extern __inline__ unsigned long scif_get_pclk_status(void)
00295 {
00296 return(AVR32_SCIF.pclksr);
00297 }
00298
00300
00301
00304
00305
00319 extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);
00320
00329 extern bool scif_is_osc_ready(scif_osc_t osc);
00330
00339 extern long int scif_stop_osc(scif_osc_t osc);
00340
00350 extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);
00351
00360 extern long int scif_configure_osc_extmode(scif_osc_t osc);
00361
00372 extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);
00373
00382 extern long int scif_enable_extosc(scif_osc_t osc);
00383
00385
00386
00389
00390
00399 extern long int scif_pll_setup(scif_pll_t pll, const scif_pll_opt_t opt);
00400
00408 extern long int scif_pll_enable(scif_pll_t pll);
00409
00410
00418 extern long int scif_pll_disable(scif_pll_t pll);
00419
00420
00428 extern long int scif_wait_for_pll_locked(scif_pll_t pll);
00429
00431
00434
00435
00448 extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);
00449
00456 #if defined (__GNUC__)
00457 __attribute__((__always_inline__))
00458 #endif
00459 extern __inline__ bool scif_is_osc32_ready()
00460 {
00461 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
00462 }
00463
00464
00471 extern long int scif_stop_osc32();
00472
00474
00475
00478
00479
00483 extern void scif_bod18_enable_irq(void);
00484
00485
00489 extern void scif_bod18_disable_irq(void);
00490
00491
00495 extern void scif_bod18_clear_irq(void);
00496
00497
00504 extern unsigned long scif_bod18_get_irq_status(void);
00505
00506
00513 extern unsigned long scif_bod18_get_irq_enable_bit(void);
00514
00515
00519 extern unsigned long scif_bod18_get_level(void);
00520
00521
00525 extern void scif_bod33_enable_irq(void);
00526
00527
00531 extern void scif_bod33_disable_irq(void);
00532
00533
00537 extern void scif_bod33_clear_irq(void);
00538
00539
00546 extern unsigned long scif_bod33_get_irq_status(void);
00547
00548
00555 extern unsigned long scif_bod33_get_irq_enable_bit(void);
00556
00557
00561 extern unsigned long scif_bod33_get_level(void);
00562
00566 extern void scif_bod50_enable_irq(void);
00567
00568
00572 extern void scif_bod50_disable_irq(void);
00573
00574
00578 extern void scif_bod50_clear_irq(void);
00579
00580
00587 extern unsigned long scif_bod50_get_irq_status(void);
00588
00589
00596 extern unsigned long scif_bod50_get_irq_enable_bit(void);
00597
00598
00602 extern unsigned long scif_bod50_get_level(void);
00603
00605
00606
00609
00610
00611
00613
00616
00617
00620 extern void scif_start_rc8M(void);
00621
00624 extern void scif_stop_rc8M(void);
00625
00626
00629
00630
00633 extern void scif_start_rc120M(void);
00634
00637 extern void scif_stop_rc120M(void);
00638
00640
00641
00644
00645
00655 extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);
00656
00668 extern long int scif_stop_gclk(unsigned int gclk);
00669
00684 extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);
00685
00694 extern long int scif_gc_enable(unsigned int gclk);
00695
00697
00698
00701
00702
00708 extern unsigned long scif_read_gplp(unsigned long gplp);
00709
00710
00716 extern void scif_write_gplp(int gplp, unsigned long value);
00717
00719
00720
00723
00724
00725
00732 #if defined (__GNUC__)
00733 __attribute__((__always_inline__))
00734 #endif
00735 extern __inline__ void scif_temperature_sensor_enable()
00736 {
00737
00738 SCIF_UNLOCK(AVR32_SCIF_TSENS);
00739 AVR32_SCIF.tsens = AVR32_SCIF_TSENS_EN_MASK;
00740 }
00741
00748 #if defined (__GNUC__)
00749 __attribute__((__always_inline__))
00750 #endif
00751 extern __inline__ void scif_temperature_sensor_disable()
00752 {
00753
00754 SCIF_UNLOCK(AVR32_SCIF_TSENS);
00755 AVR32_SCIF.tsens = ~AVR32_SCIF_TSENS_EN_MASK;
00756 }
00757
00759
00760
00761 #ifdef __cplusplus
00762 }
00763 #endif
00764
00765 #endif // _SCIF_UC3C_H_