scif_uc3l.c File Reference


Detailed Description

System Control InterFace(SCIF) driver.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file scif_uc3l.c.

#include "compiler.h"
#include "scif_uc3l.h"

Go to the source code of this file.

Data Structures

union  u_avr32_scif_dfll0conf_t
union  u_avr32_scif_dfll0ssg_t
union  u_avr32_scif_oscctrl0_t
union  u_avr32_scif_oscctrl32_t

Defines

#define SCIF_DFLL_COARSE_MAX   (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
#define SCIF_DFLL_FINE_HALF   (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))
#define SCIF_DFLL_FINE_MAX   (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)

Enumerations

enum  scif_dfll_mode_t { SCIF_DFLL0_MODE_OPENLOOP = 0, SCIF_DFLL0_MODE_CLOSEDLOOP }
 DFLL Control Functions. More...

Functions

long int scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal)
 Configure an oscillator in crystal mode.
long int scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg)
 Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
long int scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig)
 Configure and start the DFLL0 in closed loop mode.
long int scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig)
 Configure and start the DFLL0 in open loop mode.
long int scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz)
 Automatic configuration and start of the DFLL0 in open loop mode.
long int scif_dfll0_openloop_stop (void)
 Stop the DFLL0 in open loop mode.
long int scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig)
 Update the frequency of the DFLL0 in open loop mode.
long int scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf)
 Configure and enable the SSG.
void scif_disable_rc32out (void)
 Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).
long int scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready)
 Enable an oscillator with a given startup time.
long int scif_gc_enable (unsigned int gclk)
 Enable a generic clock.
long int scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
 Setup a generic clock.
bool scif_is_osc_ready (scif_osc_t osc)
 Is an oscillator stable and ready to be used as clock source?
long int scif_pclksr_statushigh_wait (unsigned long statusMask)
 Backup Registers Functions.
long int scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt)
 Generic Clock Functions.
long int scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
 Interrupt Functions.
long int scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready)
 OSC32 Functions.
void scif_start_rc120M (void)
 Calibration Functions.
void scif_start_rc32k (void)
 32kHz internal RCosc (RC32K) Functions
long int scif_stop_gclk (unsigned int gclk)
 Stop a generic clock.
long int scif_stop_osc (scif_osc_t osc)
 Stop an oscillator.
long scif_stop_osc32 ()
 Stop the OSC32 oscillator.
void scif_stop_rc120M (void)
 Stop the 120MHz internal RCosc (RC120M) clock.
void scif_stop_rc32k (void)
 Stop the 32kHz internal RCosc (RC32K) clock.


Define Documentation

#define SCIF_DFLL_COARSE_MAX   (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)

Definition at line 408 of file scif_uc3l.c.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_FINE_HALF   (1 << (AVR32_SCIF_DFLL0CONF_FINE_SIZE-1))

Definition at line 410 of file scif_uc3l.c.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_FINE_MAX   (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)

Definition at line 409 of file scif_uc3l.c.

Referenced by scif_dfll0_openloop_start_auto().


Enumeration Type Documentation

DFLL Control Functions.

The different DFLL0 modes

Enumerator:
SCIF_DFLL0_MODE_OPENLOOP 
SCIF_DFLL0_MODE_CLOSEDLOOP 

Definition at line 352 of file scif_uc3l.c.


Function Documentation

long int scif_configure_osc_crystalmode ( scif_osc_t  osc,
unsigned int  fcrystal 
)

Configure an oscillator in crystal mode.

Parameters:
osc The oscillator to configure [INPUT]
fcrystal Crystal frequency (Hz) [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully configured.
<0 Error configuring the oscillator.

Definition at line 195 of file scif_uc3l.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC0, SCIF_OSC1, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.

00196 {
00197 //# Implementation note: this code doesn't consider the osc input parameter
00198 //# because UC3L devices only implement OSC0.
00199   u_avr32_scif_oscctrl0_t   u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00200   
00201   // Configure the oscillator mode to crystal and set the gain according to the
00202   // cyrstal frequency.
00203   u_avr32_scif_oscctrl0.OSCCTRL0.mode = SCIF_OSC_MODE_2PIN_CRYSTAL;
00204   u_avr32_scif_oscctrl0.OSCCTRL0.gain = (fcrystal <  900000) ? AVR32_SCIF_OSCCTRL0_GAIN_G0 :
00205                                         (fcrystal < 3000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G1 :
00206                                         (fcrystal < 8000000) ? AVR32_SCIF_OSCCTRL0_GAIN_G2 :
00207                                                                AVR32_SCIF_OSCCTRL0_GAIN_G3;
00208   AVR32_ENTER_CRITICAL_REGION( );
00209   // Unlock the write-protected OSCCTRL0 register
00210   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00211   // Write
00212   AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00213   AVR32_LEAVE_CRITICAL_REGION( );
00214   // Add here after support for OSC1 for devices that implement OSC1.
00215 
00216   return PASS;
00217 }

long int scif_dfll0_closedloop_configure_and_start ( const scif_gclk_opt_t gc_dfllif_ref_opt,
unsigned long long  target_freq_hz,
bool  enable_ssg 
)

Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.

Note:
Configures and enables the generic clock CLK_DFLLIF_REF to serve as the main reference.

This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.

Parameters:
gc_dfllif_ref_opt The settings for the CLK_DFLLIF_REF generic clock [INPUT]
target_freq_hz The target frequency (in Hz) [INPUT]
enable_ssg Enable/disable the SSG feature [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 600 of file scif_uc3l.c.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::maxstep, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.

00603 {
00604   scif_dfll_closedloop_conf_t DfllConfig;
00605   int gc_source_clock_freq_hz;
00606 
00607   // This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock:
00608   // SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K,
00609   // SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.
00610   if(SCIF_GCCTRL_SLOWCLOCK == gc_dfllif_ref_opt->clock_source)
00611     gc_source_clock_freq_hz = SCIF_SLOWCLOCK_FREQ_HZ;
00612   else if((SCIF_GCCTRL_OSC32K == gc_dfllif_ref_opt->clock_source) || (SCIF_GCCTRL_RC32K == gc_dfllif_ref_opt->clock_source))
00613     gc_source_clock_freq_hz = SCIF_RC32K_FREQ_HZ;
00614   else if(SCIF_GCCTRL_OSC0 == gc_dfllif_ref_opt->clock_source)
00615     gc_source_clock_freq_hz = gc_dfllif_ref_opt->extosc_f;
00616   else if(SCIF_GCCTRL_RC120M == gc_dfllif_ref_opt->clock_source)
00617     gc_source_clock_freq_hz = SCIF_RC120M_FREQ_HZ;
00618   else if(SCIF_GCCTRL_CLK1K == gc_dfllif_ref_opt->clock_source)
00619     gc_source_clock_freq_hz = 1000;
00620   else
00621     return -1;
00622 
00623   // Configure and start the DFLL main reference generic clock (CLK_DFLLIF_REF).
00624   if(scif_dfll0_closedloop_mainref_gc_enable(gc_dfllif_ref_opt))
00625     return(-1);
00626 
00627   // Configure the DFLL.
00628   // The coarse value (= (dfll_f - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ))
00629   DfllConfig.coarse = ((unsigned long long)(target_freq_hz - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
00630 
00631   // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the
00632   // DFLL main reference generic clock)
00633   if(0 == gc_dfllif_ref_opt->diven)
00634     DfllConfig.fmul = ((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz;
00635   else
00636     DfllConfig.fmul = ((((unsigned long long)target_freq_hz<<16)/gc_source_clock_freq_hz)<<1)*(1+gc_dfllif_ref_opt->divider);
00637 
00638   // The maxstep value
00639 #if (defined(__GNUC__) \
00640       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00641   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00642       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00643       // UC3L revC or later
00644   DfllConfig.maxstep = 0x0040004;
00645 #else
00646       // UC3L revB
00647       //+ Errata UC3L revB: 35.2.7 SCIF.12 DFLLIF indicates coarse lock too early
00648       //+ The DFLLIF might indicate coarse lock too early, the DFLL will lose
00649       //+ coarse lock and regain it later.
00650       //+ Fix/Workaround
00651       //+ Use max step size (DFLL0MAXSTEP.MAXSTEP) of 4 or higher.
00652   DfllConfig.maxstep = 0x0040004;
00653 #endif
00654 
00655   // Dithering disabled.
00656       //+ Errata UC3L revB: 35.2.7 SCIF.13 DFLLIF dithering does not work
00657       //+ The DFLLIF dithering does not work.
00658       //+ Fix/Workaround
00659       //+ None.
00660 
00661   // Configure and start the DFLL0 in closed loop mode.
00662   if(scif_dfll0_closedloop_start(&DfllConfig))
00663     return -1;
00664 
00665   // TODO: Future implementation note: add use of the generic clock CLK_DFLLIF_DITHER
00666   // as a reference for the SSG feature.
00667   if(TRUE == enable_ssg)
00668   {
00669   ;
00670   }
00671   return PASS;
00672 }

long int scif_dfll0_closedloop_start ( const scif_dfll_closedloop_conf_t pdfllconfig  ) 

Configure and start the DFLL0 in closed loop mode.

Note:
The main reference generic clock must have previously been started.
Parameters:
pdfllconfig The DFLL parameters in closed loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 536 of file scif_uc3l.c.

References scif_dfll_closedloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::maxstep, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by local_start_dfll_clock(), and scif_dfll0_closedloop_configure_and_start().

00537 {
00538   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00539 
00540 
00541 #ifdef AVR32SFW_INPUT_CHECK
00542   if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00543     return -1;
00544   if((pdfllconfig->maxstep >> AVR32_SCIF_DFLL0STEP_MAXSTEP_SIZE))
00545     return -1;
00546 #endif
00547 
00548   // Enable the DFLL0: DFLL0CONF.EN=1
00549   u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00550   AVR32_ENTER_CRITICAL_REGION( );
00551   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00552   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00553   AVR32_LEAVE_CRITICAL_REGION( );
00554 
00555   // Wait for PCLKSR.DFLL0RDY is high
00556   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00557     return -1;
00558     
00559   // Set the maxstep
00560   AVR32_ENTER_CRITICAL_REGION( );
00561   SCIF_UNLOCK(AVR32_SCIF_MAXSTEP);
00562   AVR32_SCIF.dfll0step = (pdfllconfig->maxstep << AVR32_SCIF_DFLL0STEP_MAXSTEP_OFFSET)&AVR32_SCIF_DFLL0STEP_MAXSTEP_MASK;
00563   AVR32_LEAVE_CRITICAL_REGION( );
00564   
00565   // Wait for PCLKSR.DFLL0RDY is high
00566   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00567     return -1;
00568   
00569   // Set the fmul
00570   AVR32_ENTER_CRITICAL_REGION( );
00571   SCIF_UNLOCK(AVR32_SCIF_DFLL0FMUL);
00572   AVR32_SCIF.dfll0fmul = (pdfllconfig->fmul << AVR32_SCIF_DFLL0FMUL_FMUL_OFFSET)&AVR32_SCIF_DFLL0FMUL_FMUL_MASK;
00573   AVR32_LEAVE_CRITICAL_REGION( );
00574   
00575   // Wait for PCLKSR.DFLL0RDY is high
00576   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00577     return -1;
00578 
00579   // Set the DFLL0 to operate in closed-loop mode: DFLL0CONF.MODE=1
00580   u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_CLOSEDLOOP;
00581   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00582   AVR32_ENTER_CRITICAL_REGION( );
00583   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00584   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00585   AVR32_LEAVE_CRITICAL_REGION( );
00586 
00587   // Wait for PCLKSR.DFLL0RDY is high
00588   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00589     return -1;
00590     
00591   // Wait until the DFLL is locked on Fine value, and is ready to be selected as
00592   // clock source with a highly accurate output clock.
00593   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0LOCKF_MASK))
00594     return -1;
00595     
00596   return PASS;
00597 }

long int scif_dfll0_openloop_start ( const scif_dfll_openloop_conf_t pdfllconfig  ) 

Configure and start the DFLL0 in open loop mode.

Parameters:
pdfllconfig The DFLL parameters in open loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 358 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_openloop_start_auto().

00359 {
00360   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00361 
00362 
00363 #ifdef AVR32SFW_INPUT_CHECK
00364   if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00365     return -1;
00366   if((pdfllconfig->coarse >> AVR32_SCIF_DFLL0CONF_COARSE_SIZE))
00367     return -1;
00368 #endif
00369 
00370   // Enable the DFLL0: DFLL0CONF.EN=1
00371   u_avr32_scif_dfll0conf.DFLL0CONF.en = ENABLE;
00372   AVR32_ENTER_CRITICAL_REGION( );
00373   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00374   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00375   AVR32_LEAVE_CRITICAL_REGION( );
00376   
00377   // Wait for PCLKSR.DFLL0RDY is high
00378   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00379     return -1;
00380 
00381   // Set the DFLL0 to operate in open mode: DFLL0CONF.MODE=0
00382   u_avr32_scif_dfll0conf.DFLL0CONF.mode = SCIF_DFLL0_MODE_OPENLOOP;
00383   AVR32_ENTER_CRITICAL_REGION( );
00384   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00385   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00386   AVR32_LEAVE_CRITICAL_REGION( );
00387   
00388   // Wait for PCLKSR.DFLL0RDY is high
00389   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00390     return -1;
00391   
00392   // Write DFLL0CONF.COARSE & DFLL0CONF.FINE
00393   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00394   u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00395   AVR32_ENTER_CRITICAL_REGION( );
00396   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00397   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00398   AVR32_LEAVE_CRITICAL_REGION( );
00399 
00400   // Wait for PCLKSR.DFLL0RDY is high
00401   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00402     return -1;
00403   
00404   return PASS;
00405 }

long int scif_dfll0_openloop_start_auto ( unsigned long  TargetFreqkHz  ) 

Automatic configuration and start of the DFLL0 in open loop mode.

Parameters:
TargetFreqkHz The DFLL target frequency (in kHz) [INPUT]
Returns:
Status.
Return values:
0 DFLL0 configured and started successfully.
<0 Error.

Definition at line 411 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.

00412 {
00413   scif_dfll_openloop_conf_t Dfll0Conf;
00414   unsigned long             Coarse;
00415   unsigned long             Fine;
00416   unsigned long             CoarseFreq;
00417   unsigned long             DeltaFreq;
00418 
00419 
00420 #ifdef AVR32SFW_INPUT_CHECK
00421   if((TargetFreqkHz < SCIF_DFLL_MINFREQ_KHZ) || (TargetFreqkHz > SCIF_DFLL_MAXFREQ_KHZ))
00422     return -1;
00423 #endif
00424 
00425   //**
00426   //** Dynamically compute the COARSE and FINE values.
00427   //**
00428   // Fdfll = (Fmin+(Fmax-Fmin)*(COARSE/0xFF))*(1+X*(FINE-0x100)/0x1FF)=CoarseFreq*(1+X*(FINE-0x100)/0x1FF)
00429 
00430   // Compute the COARSE value.
00431   Coarse = ((TargetFreqkHz - SCIF_DFLL_MINFREQ_KHZ)*SCIF_DFLL_COARSE_MAX)/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ);
00432   // Compute the COARSE DFLL frequency.
00433   CoarseFreq = SCIF_DFLL_MINFREQ_KHZ + (((SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ)/SCIF_DFLL_COARSE_MAX)*Coarse);
00434   // Compute the coarse error.
00435   DeltaFreq = TargetFreqkHz - CoarseFreq;
00436   // Compute the FINE value.
00437   // Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*10/CoarseFreq) + SCIF_DFLL_FINE_HALF;
00438   // Theorical equation don't work on silicon: the best was to use X=5/2 to
00439   // find FINE, then do FINE/4.
00440   Fine = ((DeltaFreq*SCIF_DFLL_FINE_MAX)*2/CoarseFreq*5) + SCIF_DFLL_FINE_HALF;
00441   Fine >>=2;
00442 
00443   Dfll0Conf.coarse = Coarse;
00444   Dfll0Conf.fine = Fine;
00445   return(scif_dfll0_openloop_start(&Dfll0Conf));
00446 }

long int scif_dfll0_openloop_stop ( void   ) 

Stop the DFLL0 in open loop mode.

Returns:
Status.
Return values:
0 DFLL0 successfully stopped.
<0 Error.

Definition at line 480 of file scif_uc3l.c.

References u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00481 {
00482   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00483   
00484     
00485   // Before disabling the DFLL, the output freq of the DFLL should be set to a 
00486   // minimum: set COARSE to 0x00.
00487 
00488   // Wait for PCLKSR.DFLL0RDY is high
00489   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00490     return -1;
00491   
00492   // Write DFLL0CONF.COARSE
00493   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = 0;
00494   AVR32_ENTER_CRITICAL_REGION( );
00495   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00496   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00497   AVR32_LEAVE_CRITICAL_REGION( );
00498   
00499   // Wait for PCLKSR.DFLL0RDY is high
00500   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00501     return -1;
00502     
00503   // Disable the DFLL
00504   u_avr32_scif_dfll0conf.DFLL0CONF.en = 0;
00505   AVR32_ENTER_CRITICAL_REGION( );
00506   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00507   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00508   AVR32_LEAVE_CRITICAL_REGION( );
00509   
00510   // Wait for PCLKSR.DFLL0RDY is high
00511   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00512     return -1;
00513     
00514   return PASS;
00515 }

long int scif_dfll0_openloop_updatefreq ( const scif_dfll_openloop_conf_t pdfllconfig  ) 

Update the frequency of the DFLL0 in open loop mode.

Parameters:
pdfllconfig The DFLL parameters in open loop mode [INPUT]
Returns:
Status.
Return values:
0 DFLL0 frequency updated successfully.
<0 Error.

Definition at line 448 of file scif_uc3l.c.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00449 {
00450   u_avr32_scif_dfll0conf_t  u_avr32_scif_dfll0conf = {AVR32_SCIF.dfll0conf};
00451 
00452 
00453 #ifdef AVR32SFW_INPUT_CHECK
00454   if((pdfllconfig->fine >> AVR32_SCIF_DFLL0CONF_FINE_SIZE))
00455     return -1;
00456 #endif
00457 
00458   // It is assumed that the DFLL is enabled and operates in open-loop mode.
00459 
00460   // Wait for PCLKSR.DFLL0RDY is high
00461   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00462     return -1;
00463 
00464   // Write DFLL0CONF.COARSE & DFLL0CONF.FINE
00465   u_avr32_scif_dfll0conf.DFLL0CONF.coarse = pdfllconfig->coarse;
00466   u_avr32_scif_dfll0conf.DFLL0CONF.fine = pdfllconfig->fine;
00467   AVR32_ENTER_CRITICAL_REGION( );
00468   SCIF_UNLOCK(AVR32_SCIF_DFLL0CONF);
00469   AVR32_SCIF.dfll0conf = u_avr32_scif_dfll0conf.dfll0conf;
00470   AVR32_LEAVE_CRITICAL_REGION( );
00471 
00472   // Wait for PCLKSR.DFLL0RDY is high
00473   if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_DFLL0RDY_MASK))
00474     return -1;
00475 
00476   return PASS;
00477 }

long int scif_dfll0_ssg_enable ( scif_dfll_ssg_conf_t pssg_conf  ) 

Configure and enable the SSG.

Note:
The SSG reference generic clock must have previously been enabled.
Parameters:
pssg_conf The settings for the SCIF.DFLL0SSG register [INPUT]
Returns:
Status.
Return values:
0 SSG Generic clock configured and started successfully.
<0 Error.

Definition at line 518 of file scif_uc3l.c.

References scif_dfll_ssg_conf_t::amplitude, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.

00519 {
00520   u_avr32_scif_dfll0ssg_t  u_avr32_scif_dfll0ssg = {AVR32_SCIF.dfll0ssg};
00521   
00522 
00523   u_avr32_scif_dfll0ssg.DFLL0SSG.en = ENABLE;
00524   u_avr32_scif_dfll0ssg.DFLL0SSG.prbs = pssg_conf->use_random;
00525   u_avr32_scif_dfll0ssg.DFLL0SSG.amplitude = pssg_conf->amplitude;
00526   u_avr32_scif_dfll0ssg.DFLL0SSG.stepsize = pssg_conf->step_size;
00527   AVR32_ENTER_CRITICAL_REGION( );
00528   SCIF_UNLOCK(AVR32_SCIF_DFLL0SSG);
00529   AVR32_SCIF.dfll0ssg = u_avr32_scif_dfll0ssg.dfll0ssg;
00530   AVR32_LEAVE_CRITICAL_REGION( );
00531 
00532   return PASS;
00533 }

void scif_disable_rc32out ( void   ) 

Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).

Definition at line 735 of file scif_uc3l.c.

Referenced by scif_start_osc32().

00736 {
00737   unsigned long temp;
00738   AVR32_ENTER_CRITICAL_REGION( );
00739   temp = AVR32_PM.ppcr & (~AVR32_PM_PPCR_FRC32_MASK);
00740   // Unforce the RC32 signal from being output on the dedicated pin (PB04 on revB, PA20 on revC and later).
00741   AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
00742   AVR32_PM.ppcr = temp;
00743   AVR32_LEAVE_CRITICAL_REGION( );
00744 }

long int scif_enable_osc ( scif_osc_t  osc,
unsigned int  startup,
bool  wait_for_ready 
)

Enable an oscillator with a given startup time.

Parameters:
osc The oscillator to configure [INPUT]
startup Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT]
wait_for_ready Wait for the oscillator to be stable before return [INPUT]
Returns:
Status.
Return values:
0 Oscillator successfully started
<0 Error starting the oscillator.

Definition at line 220 of file scif_uc3l.c.

References u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

00221 {
00222 //# Implementation note: this code doesn't consider the osc input parameter
00223 //# because UC3L devices only implement OSC0.
00224   u_avr32_scif_oscctrl0_t   u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00225 
00226 
00227   // Configure the oscillator startup and enable the osc.
00228   u_avr32_scif_oscctrl0.OSCCTRL0.startup = startup;
00229   u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00230   AVR32_ENTER_CRITICAL_REGION( );
00231   // Unlock the write-protected OSCCTRL0 register
00232   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00233   // Write
00234   AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00235   AVR32_LEAVE_CRITICAL_REGION( );
00236 
00237   if(true == wait_for_ready)
00238   {
00239     // Wait until OSC0 is stable and ready to be used.
00240     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00241       return -1;
00242   }
00243 
00244   return PASS;
00245 }

long int scif_gc_enable ( unsigned int  gclk  ) 

Enable a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 853 of file scif_uc3l.c.

00854 {
00855 #ifdef AVR32SFW_INPUT_CHECK
00856   // Check that the generic clock number is correct
00857   if( gclk > AVR32_SCIF_GCLK_NUM )
00858   {
00859     return -1;
00860   }
00861 #endif  // AVR32SFW_INPUT_CHECK
00862 
00863   // If the generic clock is already enabled, do nothing.
00864   if(!(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK))
00865     AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00866     
00867   return PASS;
00868 }

long int scif_gc_setup ( unsigned int  gclk,
scif_gcctrl_oscsel_t  clk_src,
unsigned int  diven,
unsigned int  divfactor 
)

Setup a generic clock.

Parameters:
gclk generic clock number (0 for gc0...)
clk_src The input clock source to use for the generic clock
diven Generic clock divisor enable
divfactor Generic clock divisor
Note:
If the generic clock is already enabled, this function will disable it, apply the configuration then restart the generic clock.
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 805 of file scif_uc3l.c.

References SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().

00806 {
00807   int restart_gc = false;
00808   
00809   
00810   // Change the division factor to conform to the equation: fgclk = fsrc/divfactor = fsrc/(2*(div+1))
00811   divfactor = (divfactor>>1) -1;
00812 
00813 #ifdef AVR32SFW_INPUT_CHECK
00814   // Check that the generic clock number is correct
00815   if( gclk > AVR32_SCIF_GCLK_NUM )
00816   {
00817     return -1;
00818   }
00819   // Check that the clock source for the generic clock is correct.
00820   if(( clk_src >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( clk_src < 0 ))
00821   {
00822     return -1;
00823   }
00824   // Check that the required division factor is correct.
00825   if(diven)
00826   {
00827     if(divfactor >= (1<<AVR32_SCIF_GCCTRL_DIV_SIZE))
00828       return -1;
00829   }
00830 #endif  // AVR32SFW_INPUT_CHECK
00831 
00832   // If the generic clock is already enabled, disable it before changing its setup.
00833   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00834   {
00835     restart_gc = true;
00836     if(scif_stop_gclk(gclk) < 0)
00837       return -1;  // Could not stop the generic clock.
00838   }
00839 
00840   // Setup the generic clock.
00841   AVR32_SCIF.gcctrl[gclk] = ((divfactor << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00842                             |((diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00843                             |((clk_src << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK);
00844                             
00845   // Restart the gc if it previously was enabled.
00846   if(true == restart_gc)
00847     AVR32_SCIF.gcctrl[gclk] |= (AVR32_SCIF_GCCTRL_CEN_MASK);
00848 
00849   return PASS;
00850 }

bool scif_is_osc_ready ( scif_osc_t  osc  ) 

Is an oscillator stable and ready to be used as clock source?

Parameters:
osc The oscillator [INPUT]
Returns:
Status.
Return values:
true oscillator stable and ready
false oscillator not enabled or not ready.

Definition at line 169 of file scif_uc3l.c.

References SCIF_OSC0.

00170 {
00171 //# Implementation note: this code doesn't consider the osc input parameter
00172 //# because UC3L devices only implement OSC0.
00173   return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC0RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC0RDY_OFFSET);
00174 }

long int scif_pclksr_statushigh_wait ( unsigned long  statusMask  ) 

Backup Registers Functions.

Wait for a status high in the Power and Clocks status register.

Misc

Wait for a status high in the Power and Clocks status register.

Parameters:
statusMask Mask field of the status to poll [INPUT]
Returns:
Status.
Return values:
0 Status is high.
<0 SCIF_POLL_TIMEOUT Timeout expired before the status was high.

Definition at line 887 of file scif_uc3l.c.

References SCIF_POLL_TIMEOUT.

00888 {
00889   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00890   
00891   while(!(AVR32_SCIF.pclksr & statusMask))
00892   {
00893     if(--timeout == 0)
00894       return -1;
00895   }
00896   return PASS;
00897 }

long int scif_start_gclk ( unsigned int  gclk,
const scif_gclk_opt_t opt 
)

Generic Clock Functions.

Setup and start a generic clock.

Definition at line 750 of file scif_uc3l.c.

References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, and SCIF_GCCTRL_OSCSEL_INVALID.

00751 {
00752 #ifdef AVR32SFW_INPUT_CHECK
00753   // Check that the generic clock number is correct
00754   if( gclk > AVR32_SCIF_GCLK_NUM )
00755   {
00756     return -1;
00757   }
00758   // Check that the clock source for the generic clock is correct.
00759   if(( opt->clock_source >= SCIF_GCCTRL_OSCSEL_INVALID ) || ( opt->clock_source < 0 ))
00760   {
00761     return -1;
00762   }
00763 #endif  // AVR32SFW_INPUT_CHECK
00764 
00765   // If the generic clock is already enabled, return an error.
00766   if(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00767     return -1;
00768 
00769   // Configure & start the generic clock.
00770   AVR32_SCIF.gcctrl[gclk] = ((opt->divider << AVR32_SCIF_GCCTRL_DIV_OFFSET)&AVR32_SCIF_GCCTRL_DIV_MASK)
00771                             |((opt->diven << AVR32_SCIF_GCCTRL_DIVEN_OFFSET)&AVR32_SCIF_GCCTRL_DIVEN_MASK)
00772                             |((opt->clock_source << AVR32_SCIF_GCCTRL_OSCSEL_OFFSET)&AVR32_SCIF_GCCTRL_OSCSEL_MASK)
00773                             |(AVR32_SCIF_GCCTRL_CEN_MASK);
00774 
00775   return PASS;
00776 }

long int scif_start_osc ( scif_osc_t  osc,
const scif_osc_opt_t opt,
bool  wait_for_ready 
)

Interrupt Functions.

Configure and start an OSC0/OSC1 oscillator.

Power and Clocks Status Functions OSC0/OSC1 Functions

Definition at line 114 of file scif_uc3l.c.

References scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl_t::OSCCTRL, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC0, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.

00115 {
00116 //# Implementation note: this code doesn't consider the osc input parameter
00117 //# because UC3L devices only implement OSC0.
00118   u_avr32_scif_oscctrl0_t   u_avr32_scif_oscctrl0 = {AVR32_SCIF.oscctrl0};
00119   
00120   
00121 #ifdef AVR32SFW_INPUT_CHECK
00122   // Check that the input frequency is in the supported frequency range.
00123   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00124       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00125   {
00126     return -1;
00127   }
00128   // Check : for OSC0/OSC1, only 2 modes are supported
00129   if( (opt->mode != SCIF_OSC_MODE_EXT_CLK)
00130       && (opt->mode != SCIF_OSC_MODE_2PIN_CRYSTAL))
00131   {
00132     return -1;
00133   }
00134   // Check that the startup value is in the supported range.
00135   if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL0_STARTUP_16384_RCOSC)
00136   {
00137     return -1;
00138   }
00139   // Check that the gain value is in the supported range.
00140   if(opt->gain > AVR32_SCIF_OSCCTRL0_GAIN_G3)
00141   {
00142     return -1;
00143   }
00144 #endif  // AVR32SFW_INPUT_CHECK
00145 
00146   // Configure & start OSC0.
00147   u_avr32_scif_oscctrl0.OSCCTRL0.mode = opt->mode;
00148   u_avr32_scif_oscctrl0.OSCCTRL0.gain = opt->gain;
00149   u_avr32_scif_oscctrl0.OSCCTRL0.startup = opt->startup;
00150   u_avr32_scif_oscctrl0.OSCCTRL0.oscen = ENABLE;
00151   AVR32_ENTER_CRITICAL_REGION( );
00152   // Unlock the write-protected OSCCTRL0 register
00153   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00154   // Write
00155   AVR32_SCIF.oscctrl0 = u_avr32_scif_oscctrl0.oscctrl0;
00156   AVR32_LEAVE_CRITICAL_REGION( );
00157 
00158   if(true == wait_for_ready)
00159   {
00160     // Wait until OSC0 is stable and ready to be used.
00161     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC0RDY_MASK))
00162       return -1;
00163   }
00164 
00165   return PASS;
00166 }

long int scif_start_osc32 ( const scif_osc32_opt_t opt,
bool  wait_for_ready 
)

OSC32 Functions.

Configure and start the OSC32 oscillator.

Definition at line 252 of file scif_uc3l.c.

References scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, scif_osc32_opt_t::freq_hz, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::OSCCTRL32, u_avr32_scif_oscctrl32_t::oscctrl32, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, SCIF_OSC_MODE_NOT_SUPPORTED_1, SCIF_OSC_MODE_NOT_SUPPORTED_2, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.

00253 {
00254   u_avr32_scif_oscctrl32_t  u_avr32_scif_oscctrl32 = {AVR32_SCIF.oscctrl32};
00255   
00256   
00257 #ifdef AVR32SFW_INPUT_CHECK
00258   // Check that the input frequency is in the supported frequency range.
00259   if( (opt->freq_hz < SCIF_EXT_CRYSTAL_MIN_FREQ_HZ)
00260       || (opt->freq_hz > SCIF_EXT_CRYSTAL_MAX_FREQ_HZ))
00261   {
00262     return -1;
00263   }
00264   // Check : for OSC0/OSC1, only 2 modes are supported
00265   if( (opt->mode < SCIF_OSC_MODE_EXT_CLK)
00266       || (opt->mode > SCIF_OSC_MODE_2PIN_CRYSTAL)
00267       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_1)
00268       || (opt->mode == SCIF_OSC_MODE_NOT_SUPPORTED_2) )
00269   {
00270     return -1;
00271   }
00272   // Check that the startup value is in the supported range.
00273   if(opt->startup > (unsigned char)AVR32_SCIF_OSCCTRL32_STARTUP_524288_RCOSC)
00274   {
00275     return -1;
00276   }
00277 #endif  // AVR32SFW_INPUT_CHECK
00278 
00279 #if (defined(__GNUC__) \
00280       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00281   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00282       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00283   // Note: starting from UC3L revC on, RC32K is automatically output on PA20 upon
00284   // reset, which is the pin for XOUT32_2 => we must disable this output before
00285   // setting-up the OSC32K (in case the OSC32 is connected to XIN32_2/XOUT32_2).
00286   scif_disable_rc32out();
00287 #endif
00288 
00289   // Configure & start OSC32.
00290   u_avr32_scif_oscctrl32.OSCCTRL32.mode = opt->mode;
00291   u_avr32_scif_oscctrl32.OSCCTRL32.pinsel = opt->pinsel;
00292   u_avr32_scif_oscctrl32.OSCCTRL32.en32k = opt->en32k;
00293   u_avr32_scif_oscctrl32.OSCCTRL32.en1k = opt->en1k;
00294   u_avr32_scif_oscctrl32.OSCCTRL32.startup = opt->startup;
00295   u_avr32_scif_oscctrl32.OSCCTRL32.osc32en = ENABLE;
00296 #if (defined(__GNUC__) \
00297       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00298   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00299       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00300   // Note: starting from UC3L revC on, the OSCCTRL32 register is protected by a lock.
00301   AVR32_ENTER_CRITICAL_REGION( );
00302   // Unlock the write-protected OSCCTRL32 register
00303   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00304 #endif
00305   // write
00306   AVR32_SCIF.oscctrl32 = u_avr32_scif_oscctrl32.oscctrl32;
00307 #if (defined(__GNUC__) \
00308       && (defined(__AVR32_UC3L064__) || defined(__AVR32_UC3L032__) || defined(__AVR32_UC3L016__))) \
00309   ||((defined(__ICCAVR32__) || defined(__AAVR32__)) \
00310       && (defined(__AT32UC3L064__) || defined(__AT32UC3L032__) || defined(__AT32UC3L016__)))
00311   // Note: starting from UC3L revC on, the OSCCTRL32 register is protected by a lock.
00312   AVR32_LEAVE_CRITICAL_REGION( );
00313 #endif
00314 
00315   if(true == wait_for_ready)
00316   {
00317     // Wait until OSC32 is stable and ready to be used.
00318     if(scif_pclksr_statushigh_wait(AVR32_SCIF_PCLKSR_OSC32RDY_MASK))
00319       return -1;
00320   }
00321   
00322   return PASS;
00323 }

void scif_start_rc120M ( void   ) 

Calibration Functions.

Start the 120MHz internal RCosc (RC120M) clock.

Critical Path Oscillator Functions 120MHz RCosc Functions

Definition at line 688 of file scif_uc3l.c.

References SCIF_UNLOCK.

00689 {
00690   AVR32_ENTER_CRITICAL_REGION( );
00691   // Unlock the write-protected RC120MCR register
00692   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00693   AVR32_SCIF.rc120mcr = AVR32_SCIF_RC120MCR_EN_MASK;
00694   AVR32_LEAVE_CRITICAL_REGION( );
00695 }

void scif_start_rc32k ( void   ) 

32kHz internal RCosc (RC32K) Functions

Start the 32kHz internal RCosc (RC32K) clock.

Definition at line 714 of file scif_uc3l.c.

References SCIF_UNLOCK.

00715 {
00716   AVR32_ENTER_CRITICAL_REGION( );
00717   // Unlock the write-protected RC32KCR register
00718   SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00719   AVR32_SCIF.rc32kcr = AVR32_SCIF_RC32KCR_EN_MASK;
00720   AVR32_LEAVE_CRITICAL_REGION( );
00721 }

long int scif_stop_gclk ( unsigned int  gclk  ) 

Stop a generic clock.

Parameters:
gclk The generic clock number to stop.
Note:
To avoid an infinite loop, this function checks the Clock enable flag SCIF_POLL_TIMEOUT times.
Returns:
Status.
Return values:
0 Success.
<0 Unable to stop generic clock.

Definition at line 779 of file scif_uc3l.c.

References SCIF_POLL_TIMEOUT.

00780 {
00781   unsigned int  timeout = SCIF_POLL_TIMEOUT;
00782   
00783 #ifdef AVR32SFW_INPUT_CHECK
00784   // Check that the generic clock number is correct
00785   if( gclk > AVR32_SCIF_GCLK_NUM )
00786   {
00787     return -1;
00788   }
00789 #endif  // AVR32SFW_INPUT_CHECK
00790 
00791   // Stop the generic clock.
00792   AVR32_SCIF.gcctrl[gclk] &= ~AVR32_SCIF_GCCTRL_CEN_MASK;
00793   
00794   // Wait until the generic clock is actually stopped.
00795   while(AVR32_SCIF.gcctrl[gclk] & AVR32_SCIF_GCCTRL_CEN_MASK)
00796   {
00797     if(--timeout == 0)
00798       return -1;
00799   }
00800   
00801   return PASS;
00802 }

long int scif_stop_osc ( scif_osc_t  osc  ) 

Stop an oscillator.

Parameters:
osc The oscillator to stop
Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 177 of file scif_uc3l.c.

References SCIF_UNLOCK.

00178 {
00179 //# Implementation note: this code doesn't consider the osc input parameter
00180 //# because UC3L devices only implement OSC0.
00181   unsigned long temp = AVR32_SCIF.oscctrl0;
00182   temp &= ~AVR32_SCIF_OSCCTRL0_OSCEN_MASK;
00183 
00184   AVR32_ENTER_CRITICAL_REGION( );
00185   // Unlock the write-protected OSCCTRL0 register
00186   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL0);
00187   // Stop OSC0.
00188   AVR32_SCIF.oscctrl0 = temp;
00189   AVR32_LEAVE_CRITICAL_REGION( );
00190 
00191   return PASS;
00192 }

long scif_stop_osc32 (  ) 

Stop the OSC32 oscillator.

Returns:
Status.
Return values:
0 Oscillator successfully stopped.
<0 An error occured when stopping the oscillator.

Definition at line 326 of file scif_uc3l.c.

References AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE, and SCIF_UNLOCK.

00327 {
00328   unsigned long temp = AVR32_SCIF.oscctrl32;
00329   temp &= ~AVR32_SCIF_OSCCTRL32_OSC32EN_MASK;
00330 
00331 #if 0
00332   AVR32_ENTER_CRITICAL_REGION( );
00333   // Unlock the write-protected OSCCTRL32 register
00334   SCIF_UNLOCK(AVR32_SCIF_OSCCTRL32);
00335 #endif
00336   // Stop OSC32.
00337   AVR32_SCIF.oscctrl32 = temp;
00338 #if 0
00339   AVR32_LEAVE_CRITICAL_REGION( );
00340 #endif
00341 
00342   return PASS;
00343 }

void scif_stop_rc120M ( void   ) 

Stop the 120MHz internal RCosc (RC120M) clock.

Definition at line 697 of file scif_uc3l.c.

References SCIF_UNLOCK.

00698 {
00699   unsigned long temp = AVR32_SCIF.rc120mcr;
00700   
00701   temp &= ~AVR32_SCIF_RC120MCR_EN_MASK;
00702   AVR32_ENTER_CRITICAL_REGION( );
00703   // Unlock the write-protected RC120MCR register
00704   SCIF_UNLOCK(AVR32_SCIF_RC120MCR);
00705   AVR32_SCIF.rc120mcr = temp;
00706   AVR32_LEAVE_CRITICAL_REGION( );
00707 }

void scif_stop_rc32k ( void   ) 

Stop the 32kHz internal RCosc (RC32K) clock.

Definition at line 723 of file scif_uc3l.c.

References SCIF_UNLOCK.

00724 {
00725   unsigned long temp = AVR32_SCIF.rc32kcr;
00726 
00727   temp &= ~AVR32_SCIF_RC32KCR_EN_MASK;
00728   AVR32_ENTER_CRITICAL_REGION( );
00729   // Unlock the write-protected RC32KCR register
00730   SCIF_UNLOCK(AVR32_SCIF_RC32KCR);
00731   AVR32_SCIF.rc32kcr = temp;
00732   AVR32_LEAVE_CRITICAL_REGION( );
00733 }


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