The AVR ONE! architecture is shown in the block diagram in Figure 5.1, “AVR ONE block diagram”
Power is supplied via the 12V DC connector. The USB port is used for host communications only, and does not draw current from the host. At the heart of the AVR ONE! mainboard is the ATmega1280 AVR microcontroller, which is coupled to an FPGA for target interface signal processing. The target interface is clocked by an external clock generator capable of providing a frequency in the range of approximately 1kHz to 64MHz. A small external SRAM is connected to the AVR MCU, and is used to store symbolic information during a debug session, while the larger, faster DDR-SDRAM is used by the FPGA as a trace message buffer only.
Communication between the AVR ONE! mainboard and the probe is done by LVDS signalling over the probe cable. The LVDS transceivers are connected to level translators that shift signals between the target's operating voltage and the internal voltage level on the AVR ONE!. The 'external' side of the level translators is connected physically to the target connector. The level translators are not powered directly from VTref, but from a buffered power source which matches the VTref voltage. The JTAG channels can be operated in the range 1.65V to 5.5V up to 33MHz, while the AUX channels are capable of operating at up to 200MHz at 3.6V.
For best results it is recommended to correctly terminate the high-speed AUX signals on the target application PCB.
For further information on how to connect the probe to the target application, see section Connecting the AVR ONE!