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00047 #include <string.h>
00048 #include "compiler.h"
00049 #include "pm.h"
00050
00051
00052 extern void flashc_set_wait_state(unsigned int wait_state);
00053 #if (defined AVR32_FLASHC_210_H_INCLUDED)
00054 extern void flashc_issue_command(unsigned int command, int page_number);
00055 #endif
00056
00057
00058 #define PM_MAX_MUL ((1 << AVR32_PM_PLL0_PLLMUL_SIZE) - 1)
00059
00060
00061 int pm_configure_clocks(pm_freq_param_t *param)
00062 {
00063
00064
00065
00066
00067
00068
00069
00070
00071
00072
00073
00074
00075
00076
00077 unsigned long in_cpu_f = param->cpu_f;
00078 unsigned long in_osc0_f = param->osc0_f;
00079 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
00080 unsigned long pll_freq, rest;
00081 Bool b_div2_pba, b_div2_cpu;
00082
00083
00084 pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
00085
00086
00087 if (in_cpu_f == in_osc0_f)
00088 {
00089 param->cpu_f = in_osc0_f;
00090 param->pba_f = in_osc0_f;
00091 return PM_FREQ_STATUS_OK;
00092 }
00093 else if (in_cpu_f < in_osc0_f)
00094 {
00095
00096 }
00097
00098 rest = in_cpu_f % in_osc0_f;
00099
00100 for (div = 1; div < 32; div++)
00101 {
00102 if ((div * rest) % in_osc0_f == 0)
00103 break;
00104 }
00105 if (div == 32)
00106 return PM_FREQ_STATUS_FAIL;
00107
00108 mul = (in_cpu_f * div) / in_osc0_f;
00109
00110 if (mul > PM_MAX_MUL)
00111 return PM_FREQ_STATUS_FAIL;
00112
00113
00114 while (!(div % 2))
00115 {
00116 div /= 2;
00117 div2_cpu++;
00118 }
00119
00120
00121
00122
00123
00124 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
00125 {
00126 if (2 * mul > PM_MAX_MUL)
00127 break;
00128 mul *= 2;
00129 div2_cpu++;
00130 }
00131
00132 if (div2_cpu != 0)
00133 {
00134 div2_cpu--;
00135 div2_en = 1;
00136 }
00137
00138 pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
00139
00140
00141 param->cpu_f = pll_freq / (1 << div2_cpu);
00142 mul--;
00143
00144 pm_pll_setup(&AVR32_PM
00145 , 0
00146 , mul
00147 , div
00148 , 0
00149 , 16
00150 );
00151
00152 pm_pll_set_option(&AVR32_PM
00153 , 0
00154
00155 , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0
00156 , div2_en
00157 , 0
00158 );
00159
00160 rest = pll_freq;
00161 while (rest > AVR32_PM_PBA_MAX_FREQ ||
00162 rest != param->pba_f)
00163 {
00164 div2_pba++;
00165 rest = pll_freq / (1 << div2_pba);
00166 if (rest < param->pba_f)
00167 break;
00168 }
00169
00170
00171 param->pba_f = pll_freq / (1 << div2_pba);
00172
00173
00174 pm_pll_enable(&AVR32_PM, 0);
00175
00176
00177 pm_wait_for_pll0_locked(&AVR32_PM);
00178
00179 if (div2_cpu)
00180 {
00181 b_div2_cpu = TRUE;
00182 div2_cpu--;
00183 }
00184 else
00185 b_div2_cpu = FALSE;
00186
00187 if (div2_pba)
00188 {
00189 b_div2_pba = TRUE;
00190 div2_pba--;
00191 }
00192 else
00193 b_div2_pba = FALSE;
00194
00195 pm_cksel(&AVR32_PM
00196 , b_div2_pba, div2_pba
00197 , b_div2_cpu, div2_cpu
00198 , b_div2_cpu, div2_cpu
00199 );
00200
00201 if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
00202 {
00203 flashc_set_wait_state(1);
00204 #if (defined AVR32_FLASHC_210_H_INCLUDED)
00205 if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
00206 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
00207 else
00208 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
00209 #endif
00210 }
00211 else
00212 {
00213 flashc_set_wait_state(0);
00214 #if (defined AVR32_FLASHC_210_H_INCLUDED)
00215 if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
00216 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
00217 else
00218 flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
00219 #endif
00220 }
00221
00222 pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
00223
00224 return PM_FREQ_STATUS_OK;
00225 }
00226
00227
00228 void pm_configure_usb_clock(void)
00229 {
00230 #if (defined __AVR32_UC3A3256__) || (defined __AVR32_UC3A3128__) || (defined __AVR32_UC3A364__) || \
00231 (defined __AVR32_UC3A3256S__) || (defined __AVR32_UC3A3128S__) || (defined __AVR32_UC3A364S__) || \
00232 (defined __AT32UC3A3256__) || (defined __AT32UC3A3128__) || (defined __AT32UC3A364__) || \
00233 (defined __AT32UC3A3256S__) || (defined __AT32UC3A3128S__) || (defined __AT32UC3A364S__)
00234
00235
00236 pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,
00237 0,
00238 0,
00239 0,
00240 0);
00241
00242
00243 pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
00244 #else
00245
00246 pm_pll_setup(&AVR32_PM, 1,
00247 7,
00248 1,
00249 0,
00250 16);
00251
00252 pm_pll_set_option(&AVR32_PM, 1,
00253 1,
00254 1,
00255 0);
00256
00257
00258 pm_pll_enable(&AVR32_PM, 1);
00259
00260
00261 pm_wait_for_pll1_locked(&AVR32_PM);
00262
00263 pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,
00264 1,
00265 1,
00266 0,
00267 0);
00268 pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
00269 #endif
00270 }