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00050 #ifndef _SSC_I2S_H_
00051 #define _SSC_I2S_H_
00052
00053 #include <avr32/io.h>
00054
00055
00056 #define SSC_I2S_TIMEOUT_VALUE 10000
00057
00058 #ifdef AVR32_SSC_330_H_INCLUDED
00059 #define AVR32_SSC_TCMR_CKS_TK_PIN 0x2
00060 #define AVR32_SSC_TCMR_START_DETECT_ANY_EDGE_TF 0x7
00061 #define AVR32_SSC_RCMR_CKS_RK_PIN 0x2
00062 #define AVR32_SSC_RCMR_CKG_NONE 0x0
00063 #define AVR32_SSC_RCMR_START_DETECT_ANY_EDGE_RF 0x7
00064 #endif
00065
00066
00068 enum
00069 {
00070 SSC_I2S_ERROR = -1,
00071 SSC_I2S_OK = 0,
00072 SSC_I2S_TIMEOUT = 1,
00073 SSC_I2S_ERROR_ARGUMENT,
00074 SSC_I2S_ERROR_RX,
00075 SSC_I2S_ERROR_TX
00076 };
00077
00079 enum
00080 {
00081 SSC_I2S_MODE_STEREO_OUT = 1,
00082 SSC_I2S_MODE_STEREO_OUT_EXT_CLK,
00083 SSC_I2S_MODE_SLAVE_STEREO_OUT,
00084 SSC_I2S_MODE_STEREO_OUT_MONO_IN,
00085 SSC_I2S_MODE_RIGHT_IN,
00086 SSC_I2S_MODE_STEREO_IN,
00087 SSC_I2S_MODE_STEREO_OUT_STEREO_IN
00088 };
00089
00090
00095 extern void ssc_i2s_reset(volatile avr32_ssc_t *ssc);
00096
00118 extern int ssc_i2s_init(volatile avr32_ssc_t *ssc,
00119 unsigned int sample_frequency,
00120 unsigned int data_bit_res,
00121 unsigned int frame_bit_res,
00122 unsigned char mode,
00123 unsigned int pba_hz);
00124
00134 extern int ssc_i2s_transfer(volatile avr32_ssc_t *ssc, unsigned int data);
00135
00141 extern void ssc_i2s_disable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask);
00142
00148 extern void ssc_i2s_enable_interrupts(volatile avr32_ssc_t *ssc, unsigned long int_mask);
00149
00156 extern unsigned long ssc_i2s_get_status(volatile avr32_ssc_t *ssc);
00157
00158
00159 #endif // _SSC_I2S_H_