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00049 #include "compiler.h"
00050 #include "usart.h"
00051
00052
00053
00056
00057
00058
00065 #if (defined __GNUC__)
00066 __attribute__((__always_inline__))
00067 #endif
00068 static __inline__ int usart_mode_is_multidrop(volatile avr32_usart_t *usart)
00069 {
00070 return ((usart->mr >> AVR32_USART_MR_PAR_OFFSET) & AVR32_USART_MR_PAR_MULTI) == AVR32_USART_MR_PAR_MULTI;
00071 }
00072
00073
00089 static int usart_set_async_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00090 {
00091 unsigned int over = (pba_hz >= 16 * baudrate) ? 16 : 8;
00092 unsigned int cd_fp = ((1 << AVR32_USART_BRGR_FP_SIZE) * pba_hz + (over * baudrate) / 2) / (over * baudrate);
00093 unsigned int cd = cd_fp >> AVR32_USART_BRGR_FP_SIZE;
00094 unsigned int fp = cd_fp & ((1 << AVR32_USART_BRGR_FP_SIZE) - 1);
00095
00096 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00097 return USART_INVALID_INPUT;
00098
00099 usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |
00100 AVR32_USART_MR_SYNC_MASK |
00101 AVR32_USART_MR_OVER_MASK)) |
00102 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00103 ((over == 16) ? AVR32_USART_MR_OVER_X16 : AVR32_USART_MR_OVER_X8) << AVR32_USART_MR_OVER_OFFSET;
00104
00105 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET |
00106 fp << AVR32_USART_BRGR_FP_OFFSET;
00107
00108 return USART_SUCCESS;
00109 }
00110
00111
00126 static int usart_set_sync_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00127 {
00128 unsigned int cd = (pba_hz + baudrate / 2) / baudrate;
00129
00130 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00131 return USART_INVALID_INPUT;
00132
00133 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00134 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00135 AVR32_USART_MR_SYNC_MASK;
00136
00137 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00138
00139 return USART_SUCCESS;
00140 }
00141
00142
00150 static int usart_set_sync_slave_baudrate(volatile avr32_usart_t *usart)
00151 {
00152 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00153 AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET |
00154 AVR32_USART_MR_SYNC_MASK;
00155
00156 return USART_SUCCESS;
00157 }
00158
00159
00173 static int usart_set_iso7816_clock(volatile avr32_usart_t *usart, unsigned int clock, unsigned long pba_hz)
00174 {
00175 unsigned int cd = (pba_hz + clock / 2) / clock;
00176
00177 if (cd < 1 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00178 return USART_INVALID_INPUT;
00179
00180 usart->mr = (usart->mr & ~(AVR32_USART_MR_USCLKS_MASK |
00181 AVR32_USART_MR_SYNC_MASK |
00182 AVR32_USART_MR_OVER_MASK)) |
00183 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET |
00184 AVR32_USART_MR_OVER_X16 << AVR32_USART_MR_OVER_OFFSET;
00185
00186 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00187
00188 return USART_SUCCESS;
00189 }
00190
00191
00192 #if defined(AVR32_USART_400_H_INCLUDED) || \
00193 defined(AVR32_USART_410_H_INCLUDED) || \
00194 defined(AVR32_USART_420_H_INCLUDED) || \
00195 defined(AVR32_USART_440_H_INCLUDED)
00196
00197
00211 static int usart_set_spi_master_baudrate(volatile avr32_usart_t *usart, unsigned int baudrate, unsigned long pba_hz)
00212 {
00213 unsigned int cd = (pba_hz + baudrate / 2) / baudrate;
00214
00215 if (cd < 4 || cd > (1 << AVR32_USART_BRGR_CD_SIZE) - 1)
00216 return USART_INVALID_INPUT;
00217
00218 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00219 AVR32_USART_MR_USCLKS_MCK << AVR32_USART_MR_USCLKS_OFFSET;
00220
00221 usart->brgr = cd << AVR32_USART_BRGR_CD_OFFSET;
00222
00223 return USART_SUCCESS;
00224 }
00225
00226
00234 static int usart_set_spi_slave_baudrate(volatile avr32_usart_t *usart)
00235 {
00236 usart->mr = (usart->mr & ~AVR32_USART_MR_USCLKS_MASK) |
00237 AVR32_USART_MR_USCLKS_SCK << AVR32_USART_MR_USCLKS_OFFSET;
00238
00239 return USART_SUCCESS;
00240 }
00241
00242
00243 #endif // USART rev. >= 4.0.0
00244
00245
00247
00248
00249
00252
00253
00254
00255 void usart_reset(volatile avr32_usart_t *usart)
00256 {
00257 Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00258
00259
00260
00261 if (global_interrupt_enabled) Disable_global_interrupt();
00262 usart->idr = 0xFFFFFFFF;
00263 usart->csr;
00264 if (global_interrupt_enabled) Enable_global_interrupt();
00265
00266
00267 usart->mr = 0;
00268 usart->rtor = 0;
00269 usart->ttgr = 0;
00270
00271
00272
00273 usart->cr = AVR32_USART_CR_RSTRX_MASK |
00274 AVR32_USART_CR_RSTTX_MASK |
00275 AVR32_USART_CR_RSTSTA_MASK |
00276 AVR32_USART_CR_RSTIT_MASK |
00277 AVR32_USART_CR_RSTNACK_MASK |
00278 #ifndef AVR32_USART_440_H_INCLUDED
00279
00280 AVR32_USART_CR_DTRDIS_MASK |
00281 #endif
00282 AVR32_USART_CR_RTSDIS_MASK;
00283 }
00284
00285
00286 int usart_init_rs232(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00287 {
00288
00289 usart_reset(usart);
00290
00291
00292 if (!opt ||
00293 opt->charlength < 5 || opt->charlength > 9 ||
00294 opt->paritytype > 7 ||
00295 opt->stopbits > 2 + 255 ||
00296 opt->channelmode > 3 ||
00297 usart_set_async_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00298 return USART_INVALID_INPUT;
00299
00300 if (opt->charlength == 9)
00301 {
00302
00303 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00304 }
00305 else
00306 {
00307
00308 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00309 }
00310
00311 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00312 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00313
00314 if (opt->stopbits > USART_2_STOPBITS)
00315 {
00316
00317 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00318
00319 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00320 }
00321 else
00322
00323 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00324
00325
00326 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00327 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00328
00329
00330
00331 usart->cr = AVR32_USART_CR_RXEN_MASK |
00332 AVR32_USART_CR_TXEN_MASK;
00333
00334 return USART_SUCCESS;
00335 }
00336
00337
00338 int usart_init_rs232_tx_only(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00339 {
00340
00341 usart_reset(usart);
00342
00343
00344 if (!opt ||
00345 opt->charlength < 5 || opt->charlength > 9 ||
00346 opt->paritytype > 7 ||
00347 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00348 opt->channelmode > 3 ||
00349 usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00350 return USART_INVALID_INPUT;
00351
00352 if (opt->charlength == 9)
00353 {
00354
00355 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00356 }
00357 else
00358 {
00359
00360 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00361 }
00362
00363 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00364 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00365
00366 if (opt->stopbits > USART_2_STOPBITS)
00367 {
00368
00369 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00370
00371 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00372 }
00373 else
00374
00375 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00376
00377
00378 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00379 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00380
00381
00382
00383
00384 usart->cr = AVR32_USART_CR_TXEN_MASK;
00385
00386 return USART_SUCCESS;
00387 }
00388
00389
00390 int usart_init_hw_handshaking(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00391 {
00392
00393 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00394 return USART_INVALID_INPUT;
00395
00396
00397 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00398 AVR32_USART_MR_MODE_HARDWARE << AVR32_USART_MR_MODE_OFFSET;
00399
00400 return USART_SUCCESS;
00401 }
00402
00403
00404 int usart_init_modem(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00405 {
00406
00407 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00408 return USART_INVALID_INPUT;
00409
00410
00411 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00412 AVR32_USART_MR_MODE_MODEM << AVR32_USART_MR_MODE_OFFSET;
00413
00414 return USART_SUCCESS;
00415 }
00416
00417
00418 int usart_init_sync_master(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00419 {
00420
00421 usart_reset(usart);
00422
00423
00424 if (!opt ||
00425 opt->charlength < 5 || opt->charlength > 9 ||
00426 opt->paritytype > 7 ||
00427 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00428 opt->channelmode > 3 ||
00429 usart_set_sync_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00430 return USART_INVALID_INPUT;
00431
00432 if (opt->charlength == 9)
00433 {
00434
00435 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00436 }
00437 else
00438 {
00439
00440 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00441 }
00442
00443 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00444 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00445
00446 if (opt->stopbits > USART_2_STOPBITS)
00447 {
00448
00449 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00450
00451 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00452 }
00453 else
00454
00455 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00456
00457
00458 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00459 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET |
00460 AVR32_USART_MR_CLKO_MASK;
00461
00462
00463
00464 usart->cr = AVR32_USART_CR_RXEN_MASK |
00465 AVR32_USART_CR_TXEN_MASK;
00466
00467 return USART_SUCCESS;
00468 }
00469
00470
00471 int usart_init_sync_slave(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00472 {
00473
00474 usart_reset(usart);
00475
00476
00477 if (!opt ||
00478 opt->charlength < 5 || opt->charlength > 9 ||
00479 opt->paritytype > 7 ||
00480 opt->stopbits == 1 || opt->stopbits > 2 + 255 ||
00481 opt->channelmode > 3 ||
00482 usart_set_sync_slave_baudrate(usart) == USART_INVALID_INPUT)
00483 return USART_INVALID_INPUT;
00484
00485 if (opt->charlength == 9)
00486 {
00487
00488 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00489 }
00490 else
00491 {
00492
00493 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00494 }
00495
00496 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00497 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET;
00498
00499 if (opt->stopbits > USART_2_STOPBITS)
00500 {
00501
00502 usart->mr |= AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET;
00503
00504 usart->ttgr = opt->stopbits - USART_2_STOPBITS;
00505 }
00506 else
00507
00508 usart->mr |= opt->stopbits << AVR32_USART_MR_NBSTOP_OFFSET;
00509
00510
00511 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00512 AVR32_USART_MR_MODE_NORMAL << AVR32_USART_MR_MODE_OFFSET;
00513
00514
00515
00516 usart->cr = AVR32_USART_CR_RXEN_MASK |
00517 AVR32_USART_CR_TXEN_MASK;
00518
00519 return USART_SUCCESS;
00520 }
00521
00522
00523 int usart_init_rs485(volatile avr32_usart_t *usart, const usart_options_t *opt, long pba_hz)
00524 {
00525
00526 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00527 return USART_INVALID_INPUT;
00528
00529
00530 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00531 AVR32_USART_MR_MODE_RS485 << AVR32_USART_MR_MODE_OFFSET;
00532
00533 return USART_SUCCESS;
00534 }
00535
00536
00537 int usart_init_IrDA(volatile avr32_usart_t *usart, const usart_options_t *opt,
00538 long pba_hz, unsigned char irda_filter)
00539 {
00540
00541 if (usart_init_rs232(usart, opt, pba_hz) == USART_INVALID_INPUT)
00542 return USART_INVALID_INPUT;
00543
00544
00545 usart->ifr = irda_filter;
00546
00547
00548 usart->mr = (usart->mr & ~AVR32_USART_MR_MODE_MASK) |
00549 AVR32_USART_MODE_IRDA << AVR32_USART_MR_MODE_OFFSET |
00550 AVR32_USART_MR_FILTER_MASK;
00551
00552 return USART_SUCCESS;
00553 }
00554
00555
00556 int usart_init_iso7816(volatile avr32_usart_t *usart, const usart_iso7816_options_t *opt, int t, long pba_hz)
00557 {
00558
00559 usart_reset(usart);
00560
00561
00562 if (!opt ||
00563 opt->paritytype > 1)
00564 return USART_INVALID_INPUT;
00565
00566 if (t == 0)
00567 {
00568
00569
00570 usart->mr = AVR32_USART_MR_MODE_ISO7816_T0 << AVR32_USART_MR_MODE_OFFSET |
00571 AVR32_USART_MR_NBSTOP_2 << AVR32_USART_MR_NBSTOP_OFFSET |
00572 opt->bit_order << AVR32_USART_MR_MSBF_OFFSET;
00573 }
00574 else if (t == 1)
00575 {
00576
00577
00578 if (opt->bit_order != 0 ||
00579 opt->max_iterations != 0)
00580 return USART_INVALID_INPUT;
00581
00582
00583
00584 usart->mr = AVR32_USART_MR_MODE_ISO7816_T1 << AVR32_USART_MR_MODE_OFFSET |
00585 AVR32_USART_MR_NBSTOP_1 << AVR32_USART_MR_NBSTOP_OFFSET;
00586 }
00587 else
00588 return USART_INVALID_INPUT;
00589
00590 if (usart_set_iso7816_clock(usart, opt->iso7816_hz, pba_hz) == USART_INVALID_INPUT)
00591 return USART_INVALID_INPUT;
00592
00593
00594 usart->fidi = opt->fidi_ratio;
00595
00596
00597 usart->mr |= opt->paritytype << AVR32_USART_MR_PAR_OFFSET |
00598 AVR32_USART_MR_CLKO_MASK |
00599 opt->inhibit_nack << AVR32_USART_MR_INACK_OFFSET |
00600 opt->dis_suc_nack << AVR32_USART_MR_DSNACK_OFFSET |
00601 opt->max_iterations << AVR32_USART_MR_MAX_ITERATION_OFFSET;
00602
00603
00604 usart_iso7816_enable_receiver(usart);
00605
00606 return USART_SUCCESS;
00607 }
00608
00609
00610 #if defined(AVR32_USART_400_H_INCLUDED) || \
00611 defined(AVR32_USART_410_H_INCLUDED) || \
00612 defined(AVR32_USART_420_H_INCLUDED) || \
00613 defined(AVR32_USART_440_H_INCLUDED)
00614
00615
00616 int usart_init_lin_master(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)
00617 {
00618
00619 usart_reset(usart);
00620
00621
00622 if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)
00623 return USART_INVALID_INPUT;
00624
00625 usart->mr |= AVR32_USART_MR_MODE_LIN_MASTER << AVR32_USART_MR_MODE_OFFSET;
00626
00627
00628
00629 usart->cr = AVR32_USART_CR_RXEN_MASK |
00630 AVR32_USART_CR_TXEN_MASK;
00631
00632 return USART_SUCCESS;
00633 }
00634
00635
00636 int usart_init_lin_slave(volatile avr32_usart_t *usart, unsigned long baudrate, long pba_hz)
00637 {
00638
00639 usart_reset(usart);
00640
00641
00642 if (usart_set_async_baudrate(usart, baudrate, pba_hz) == USART_INVALID_INPUT)
00643 return USART_INVALID_INPUT;
00644
00645 usart->mr |= AVR32_USART_MR_MODE_LIN_SLAVE << AVR32_USART_MR_MODE_OFFSET;
00646
00647
00648
00649 usart->cr = AVR32_USART_CR_RXEN_MASK |
00650 AVR32_USART_CR_TXEN_MASK;
00651
00652 return USART_SUCCESS;
00653 }
00654
00655
00656 int usart_init_spi_master(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)
00657 {
00658
00659 usart_reset(usart);
00660
00661
00662 if (!opt ||
00663 opt->charlength < 5 || opt->charlength > 9 ||
00664 opt->spimode > 3 ||
00665 opt->channelmode > 3 ||
00666 usart_set_spi_master_baudrate(usart, opt->baudrate, pba_hz) == USART_INVALID_INPUT)
00667 return USART_INVALID_INPUT;
00668
00669 if (opt->charlength == 9)
00670 {
00671
00672 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00673 }
00674 else
00675 {
00676
00677 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00678 }
00679
00680 usart->mr |= AVR32_USART_MR_MODE_SPI_MASTER << AVR32_USART_MR_MODE_OFFSET |
00681 ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |
00682 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |
00683 (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET |
00684 AVR32_USART_MR_CLKO_MASK;
00685
00686
00687
00688 usart->cr = AVR32_USART_CR_RXEN_MASK |
00689 AVR32_USART_CR_TXEN_MASK;
00690
00691 return USART_SUCCESS;
00692 }
00693
00694
00695 int usart_init_spi_slave(volatile avr32_usart_t *usart, const usart_spi_options_t *opt, long pba_hz)
00696 {
00697
00698 usart_reset(usart);
00699
00700
00701 if (!opt ||
00702 opt->charlength < 5 || opt->charlength > 9 ||
00703 opt->spimode > 3 ||
00704 opt->channelmode > 3 ||
00705 usart_set_spi_slave_baudrate(usart) == USART_INVALID_INPUT)
00706 return USART_INVALID_INPUT;
00707
00708 if (opt->charlength == 9)
00709 {
00710
00711 usart->mr |= AVR32_USART_MR_MODE9_MASK;
00712 }
00713 else
00714 {
00715
00716 usart->mr |= (opt->charlength - 5) << AVR32_USART_MR_CHRL_OFFSET;
00717 }
00718
00719 usart->mr |= AVR32_USART_MR_MODE_SPI_SLAVE << AVR32_USART_MR_MODE_OFFSET |
00720 ((opt->spimode & 0x1) ^ 0x1) << AVR32_USART_MR_SYNC_OFFSET |
00721 opt->channelmode << AVR32_USART_MR_CHMODE_OFFSET |
00722 (opt->spimode >> 1) << AVR32_USART_MR_MSBF_OFFSET;
00723
00724
00725
00726 usart->cr = AVR32_USART_CR_RXEN_MASK |
00727 AVR32_USART_CR_TXEN_MASK;
00728
00729 return USART_SUCCESS;
00730 }
00731
00732
00733 #endif // USART rev. >= 4.0.0
00734
00735
00737
00738
00739
00740 #if defined(AVR32_USART_400_H_INCLUDED) || \
00741 defined(AVR32_USART_410_H_INCLUDED) || \
00742 defined(AVR32_USART_420_H_INCLUDED) || \
00743 defined(AVR32_USART_440_H_INCLUDED)
00744
00745
00748
00749
00750
00751 int usart_spi_selectChip(volatile avr32_usart_t *usart)
00752 {
00753
00754 usart->cr = AVR32_USART_CR_RTSEN_MASK;
00755
00756 return USART_SUCCESS;
00757 }
00758
00759
00760 int usart_spi_unselectChip(volatile avr32_usart_t *usart)
00761 {
00762 int timeout = USART_DEFAULT_TIMEOUT;
00763
00764 do
00765 {
00766 if (!timeout--) return USART_FAILURE;
00767 } while (!usart_tx_empty(usart));
00768
00769
00770 usart->cr = AVR32_USART_CR_RTSDIS_MASK;
00771
00772 return USART_SUCCESS;
00773 }
00774
00775
00777
00778
00779 #endif // USART rev. >= 4.0.0
00780
00781
00782
00785
00786
00787
00788 int usart_send_address(volatile avr32_usart_t *usart, int address)
00789 {
00790
00791 if (!usart_mode_is_multidrop(usart)) return USART_MODE_FAULT;
00792
00793
00794 usart->cr = AVR32_USART_CR_SENDA_MASK;
00795
00796
00797 usart_bw_write_char(usart, address);
00798
00799 return USART_SUCCESS;
00800 }
00801
00802
00803 int usart_write_char(volatile avr32_usart_t *usart, int c)
00804 {
00805 if (usart_tx_ready(usart))
00806 {
00807 usart->thr = (c << AVR32_USART_THR_TXCHR_OFFSET) & AVR32_USART_THR_TXCHR_MASK;
00808 return USART_SUCCESS;
00809 }
00810 else
00811 return USART_TX_BUSY;
00812 }
00813
00814
00815 int usart_putchar(volatile avr32_usart_t *usart, int c)
00816 {
00817 int timeout = USART_DEFAULT_TIMEOUT;
00818
00819 if (c == '\n')
00820 {
00821 do
00822 {
00823 if (!timeout--) return USART_FAILURE;
00824 } while (usart_write_char(usart, '\r') != USART_SUCCESS);
00825
00826 timeout = USART_DEFAULT_TIMEOUT;
00827 }
00828
00829 do
00830 {
00831 if (!timeout--) return USART_FAILURE;
00832 } while (usart_write_char(usart, c) != USART_SUCCESS);
00833
00834 return USART_SUCCESS;
00835 }
00836
00837
00838 int usart_read_char(volatile avr32_usart_t *usart, int *c)
00839 {
00840
00841
00842 if (usart->csr & (AVR32_USART_CSR_OVRE_MASK |
00843 AVR32_USART_CSR_FRAME_MASK |
00844 AVR32_USART_CSR_PARE_MASK))
00845 return USART_RX_ERROR;
00846
00847
00848 if (usart_test_hit(usart))
00849 {
00850 *c = (usart->rhr & AVR32_USART_RHR_RXCHR_MASK) >> AVR32_USART_RHR_RXCHR_OFFSET;
00851 return USART_SUCCESS;
00852 }
00853 else
00854 return USART_RX_EMPTY;
00855 }
00856
00857
00858 int usart_getchar(volatile avr32_usart_t *usart)
00859 {
00860 int c, ret;
00861
00862 while ((ret = usart_read_char(usart, &c)) == USART_RX_EMPTY);
00863
00864 if (ret == USART_RX_ERROR)
00865 return USART_FAILURE;
00866
00867 return c;
00868 }
00869
00870
00871 void usart_write_line(volatile avr32_usart_t *usart, const char *string)
00872 {
00873 while (*string != '\0')
00874 usart_putchar(usart, *string++);
00875 }
00876
00877
00878 int usart_get_echo_line(volatile avr32_usart_t *usart)
00879 {
00880 int rx_char;
00881 int retval = USART_SUCCESS;
00882
00883 while (1)
00884 {
00885 rx_char = usart_getchar(usart);
00886 if (rx_char == USART_FAILURE)
00887 {
00888 usart_write_line(usart, "Error!!!\n");
00889 retval = USART_FAILURE;
00890 break;
00891 }
00892 if (rx_char == '\x03')
00893 {
00894 retval = USART_FAILURE;
00895 break;
00896 }
00897 usart_putchar(usart, rx_char);
00898 if (rx_char == '\r')
00899 {
00900 usart_putchar(usart, '\n');
00901 break;
00902 }
00903 }
00904
00905 return retval;
00906 }
00907
00908