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00046 #ifndef _SCIF_UC3L_H_
00047 #define _SCIF_UC3L_H_
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053 #include "compiler.h"
00054
00055
00056 #if defined(AVR32_SCIF_100_H_INCLUDED) || defined(AVR32_SCIF_102_H_INCLUDED)
00057
00058 #define AVR32_SCIF_GC_NO_DIV_CLOCK AVR32_GC_NO_DIV_CLOCK
00059 #endif
00060
00061 #define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001
00062 #define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000
00063 #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001
00064 #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000
00065
00066
00068 #if ((__GNUC__ && (__AVR32_UC3L016__ || __AVR32_UC3L032__ || __AVR32_UC3L064__)) \
00069 ||(__ICCAVR32__ && (__AT32UC3L016__ || __AT32UC3L032__ || __AT32UC3L064__ )))
00070
00071
00073 #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000
00075 #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000
00076
00078 typedef enum
00079 {
00080 SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW,
00081 SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32,
00082 SCIF_GCCTRL_DFLL0 = AVR32_SCIF_GC_USES_DFLL0,
00083 SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0,
00084 SCIF_GCCTRL_RC120M = AVR32_SCIF_GC_USES_RC120M,
00085 SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU,
00086 SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB,
00087 SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA,
00088 SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB,
00089 SCIF_GCCTRL_RC32K = AVR32_SCIF_GC_USES_RC32K,
00090 SCIF_GCCTRL_CRIPOSC = AVR32_SCIF_GC_USES_CRIPOSC,
00091 SCIF_GCCTRL_CLK1K = AVR32_SCIF_GC_USES_CLK_1K,
00092 SCIF_GCCTRL_OSCSEL_INVALID
00093 } scif_gcctrl_oscsel_t;
00094
00096 #define SCIF_DFLL_MINFREQ_KHZ 20000
00097 #define SCIF_DFLL_MINFREQ_HZ 20000000L
00098
00100 #define SCIF_DFLL_MAXFREQ_KHZ 150000
00101 #define SCIF_DFLL_MAXFREQ_HZ 150000000L
00102
00104 #define SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY
00105 #define SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/100)
00106
00108 #define SCIF_RC32K_FREQ_HZ 32768
00109 #define SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/100)
00110
00112 #define SCIF_RC120M_FREQ_HZ 120000000L
00113 #define SCIF_RC120M_FREQ_KHZ 120000
00114
00116 #define SCIF_OSC32_FREQ_HZ 32768
00117
00118 #endif
00119
00120
00122 #define SCIF_POLL_TIMEOUT 100000
00123
00125 #define SCIF_NOT_SUPPORTED (-10000)
00126
00127
00129 typedef enum
00130 {
00131 SCIF_OSC0 = 0,
00132 SCIF_OSC1 = 1
00133 } scif_osc_t;
00134
00136 typedef enum
00137 {
00138 SCIF_OSC_MODE_EXT_CLK = 0,
00139 SCIF_OSC_MODE_2PIN_CRYSTAL = 1,
00140 SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2,
00141 SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3,
00142 SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4,
00143 SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5,
00144 SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6,
00145 SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7
00146 } scif_osc_mode_t;
00147
00149 typedef struct
00150 {
00152 unsigned long freq_hz;
00154 scif_osc_mode_t mode;
00156 unsigned char startup;
00158 unsigned char gain;
00159 } scif_osc_opt_t;
00160
00162 typedef struct
00163 {
00165 scif_osc_mode_t mode;
00167 unsigned char startup;
00169 bool pinsel;
00171 bool en1k;
00173 bool en32k;
00174 } scif_osc32_opt_t;
00175
00176
00178 typedef struct
00179 {
00181 scif_gcctrl_oscsel_t clock_source;
00183 unsigned int divider;
00185 unsigned int diven;
00187
00188 unsigned long extosc_f;
00189 } scif_gclk_opt_t;
00190
00191
00193 typedef struct
00194 {
00195 unsigned int fine;
00196 unsigned int coarse;
00197 } scif_dfll_openloop_conf_t;
00198
00200 typedef struct
00201 {
00203 unsigned int coarse;
00205 unsigned int fmul;
00207 unsigned int maxstep;
00208 } scif_dfll_closedloop_conf_t;
00209
00211 typedef struct
00212 {
00214 unsigned int use_random;
00216 unsigned int amplitude;
00218 unsigned int step_size;
00219 } scif_dfll_ssg_conf_t;
00220
00221
00223 #define SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
00224
00227
00228
00233 #if __GNUC__
00234 __attribute__((__always_inline__))
00235 #endif
00236 extern __inline__ void scif_enable_interrupts(unsigned long mask)
00237 {
00238 AVR32_SCIF.ier = mask;
00239 }
00240
00245 #if __GNUC__
00246 __attribute__((__always_inline__))
00247 #endif
00248 extern __inline__ void scif_disable_interrupts(unsigned long mask)
00249 {
00250 AVR32_SCIF.idr = mask;
00251 }
00252
00257 #if __GNUC__
00258 __attribute__((__always_inline__))
00259 #endif
00260 extern __inline__ unsigned long scif_get_enabled_interrupts(void)
00261 {
00262 return(AVR32_SCIF.imr);
00263 }
00264
00269 #if __GNUC__
00270 __attribute__((__always_inline__))
00271 #endif
00272 extern __inline__ unsigned long scif_get_interrupts_status(void)
00273 {
00274 return(AVR32_SCIF.isr);
00275 }
00276
00281 #if __GNUC__
00282 __attribute__((__always_inline__))
00283 #endif
00284 extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
00285 {
00286 AVR32_SCIF.icr = mask;
00287 }
00288
00290
00291
00294
00295
00300 #if __GNUC__
00301 __attribute__((__always_inline__))
00302 #endif
00303 extern __inline__ unsigned long scif_get_pclk_status(void)
00304 {
00305 return(AVR32_SCIF.pclksr);
00306 }
00307
00309
00310
00313
00314
00328 extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);
00329
00338 extern bool scif_is_osc_ready(scif_osc_t osc);
00339
00348 extern long int scif_stop_osc(scif_osc_t osc);
00349
00359 extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);
00360
00371 extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);
00372
00374
00375
00378
00379
00392 extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);
00393
00400 #if __GNUC__
00401 __attribute__((__always_inline__))
00402 #endif
00403 extern __inline__ bool scif_is_osc32_ready()
00404 {
00405 return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
00406 }
00407
00411 #if __GNUC__
00412 __attribute__((__always_inline__))
00413 #endif
00414 extern __inline__ void scif_osc32_1kout_ena()
00415 {
00416 AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
00417 }
00418
00422 #if __GNUC__
00423 __attribute__((__always_inline__))
00424 #endif
00425 extern __inline__ void scif_osc32_1kout_dis()
00426 {
00427 AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
00428 }
00429
00433 #if __GNUC__
00434 __attribute__((__always_inline__))
00435 #endif
00436 extern __inline__ void scif_osc32_32kout_ena()
00437 {
00438 AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
00439 }
00440
00444 #if __GNUC__
00445 __attribute__((__always_inline__))
00446 #endif
00447 extern __inline__ void scif_osc32_32kout_dis()
00448 {
00449 AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
00450 }
00451
00458 extern long int scif_stop_osc32();
00459
00461
00462
00465
00466
00475 extern long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig);
00476
00485 extern long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz);
00486
00495 extern long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig);
00496
00505 extern long int scif_dfll0_openloop_updatefreq_auto(unsigned long TargetFreq);
00506
00513 extern long int scif_dfll0_openloop_stop(void);
00514
00526 #define scif_dfll0_ssg_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)
00527
00538 extern long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf);
00539
00548 #define scif_dfll0_closedloop_mainref_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)
00549
00560 extern long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig);
00561
00579 extern long int scif_dfll0_closedloop_configure_and_start( const scif_gclk_opt_t *gc_dfllif_ref_opt,
00580 unsigned long long target_freq_hz,
00581 bool enable_ssg);
00582
00591 #define scif_dfll0_closedloop_dither_gc_enable(pgc_conf) scif_dfll0_ssg_gc_enable(pgc_conf)
00592
00593
00594
00596
00597
00600
00601
00602
00604
00605
00608
00609
00612 extern void scif_start_rc120M(void);
00613
00616 extern void scif_stop_rc120M(void);
00617
00619
00620
00623
00624
00627 extern void scif_start_rc32k(void);
00628
00631 extern void scif_stop_rc32k(void);
00632
00636 extern void scif_disable_rc32out(void);
00637
00639
00640
00643
00644
00654 extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);
00655
00667 extern long int scif_stop_gclk(unsigned int gclk);
00668
00683 extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);
00684
00693 extern long int scif_gc_enable(unsigned int gclk);
00694
00696
00697
00700
00701
00702
00704
00705
00708
00709
00718 long int scif_pclksr_statushigh_wait(unsigned long statusMask);
00719
00721
00722 #ifdef __cplusplus
00723 }
00724 #endif
00725
00726 #endif // _SCIF_UC3L_H_