pm_example1.c File Reference


Detailed Description

Osc0 as Main clock source and Generic clock configuration and sleep mode example.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm_example1.c.

#include "board.h"
#include "gpio.h"
#include "scif_uc3l.h"
#include "pm_uc3l.h"

Go to the source code of this file.

Defines

Generic Clock Configuration
#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION
#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG
#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Functions

static void local_enable_gclk_on_gpio (volatile avr32_pm_t *pm)
static void local_switch_to_osc0 (volatile avr32_pm_t *pm)
int main (void)


Define Documentation

#define EXAMPLE_GCLK_FUNCTION   AVR32_SCIF_GCLK_1_0_FUNCTION

Definition at line 138 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().

#define EXAMPLE_GCLK_ID   AVR32_SCIF_GCLK_DFLL0_SSG

Definition at line 136 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().

#define EXAMPLE_GCLK_PIN   AVR32_SCIF_GCLK_1_0_PIN

Definition at line 137 of file pm_example1.c.

Referenced by local_enable_gclk_on_gpio().


Function Documentation

static void local_enable_gclk_on_gpio ( volatile avr32_pm_t *  pm  )  [static]

Definition at line 183 of file pm_example1.c.

References EXAMPLE_GCLK_FUNCTION, EXAMPLE_GCLK_ID, EXAMPLE_GCLK_PIN, pm_gc_enable(), and pm_gc_setup().

Referenced by main().

00184 {
00185   int gc = EXAMPLE_GCLK_ID;
00186 
00187 #if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK )
00188   // Note: for UC3L and UC3C devices, the generic clock configurations are handled by the
00189   // SCIF module.
00190   /* setup gc on Osc0, no divisor */
00191   scif_gc_setup(gc, SCIF_GCCTRL_OSC0, AVR32_SCIF_GC_NO_DIV_CLOCK, 0);
00192   
00193   /* Now enable the generic clock */
00194   scif_gc_enable(gc);
00195 #else
00196   /* setup gc on Osc0, no divisor */
00197   pm_gc_setup(pm, gc, AVR32_GC_USES_OSC, AVR32_GC_USES_OSC0, AVR32_GC_NO_DIV_CLOCK, 0);
00198 
00199   /* Now enable the generic clock */
00200   pm_gc_enable(pm,gc);
00201 #endif
00202 
00203   /* Assign a GPIO to generic clock output */
00204   gpio_enable_module_pin(EXAMPLE_GCLK_PIN, EXAMPLE_GCLK_FUNCTION);
00205   // Note that gclk0_1 is GPIO pin 51 pb19 on AT32UC3A0512 QFP144.
00206   // Note that gclk2 is GPIO pin 30 pa30 on AT32UC3B0256 QFP64.
00207   // Note that gclk1 is GPIO pin 43 pb11 on AT32UC3A3256 QFP144.
00208   // Note that gclk1 is GPIO pin 6 pa06 on AT32UC3L064 pin 10 on QFP48.
00209   // Note that gclk0 is GPIO pin 54 pb22 on AT32UC3C0512C QFP144.
00210 }

static void local_switch_to_osc0 ( volatile avr32_pm_t *  pm  )  [static]

Definition at line 154 of file pm_example1.c.

References PM_CLK_SRC_OSC0, pm_enable_clk0(), pm_enable_osc0_crystal(), pm_set_mclk_source(), and pm_switch_to_clock().

Referenced by main().

00155 {
00156 #if ( BOARD == STK600_RCUC3L0 ) || ( BOARD == UC3C_EK )
00157   // Note: for UC3L and UC3C devices, the osc configurations are handled by the SCIF module
00158   // and the synchronous clocks used to clock the main digital logic are handled
00159   // by the PM module.
00160   // 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00161   scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00162   // 2) Enable the OSC0
00163   scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00164   // 3) Set the main clock source as being OSC0.
00165   pm_set_mclk_source(PM_CLK_SRC_OSC0);
00166 #else
00167   // 1) Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
00168   pm_enable_osc0_crystal(pm, FOSC0);  // with Osc
00169   // 2) Enable the OSC0
00170   pm_enable_clk0(pm, OSC0_STARTUP);
00171   // 3) Set the main clock source as being OSC0.
00172   pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);
00173 #endif
00174   // From now on, the CPU frequency is FOSC0 Hz.
00175 }

int main ( void   ) 

Definition at line 222 of file pm_example1.c.

References local_enable_gclk_on_gpio(), local_switch_to_osc0(), and SLEEP.

00223 {
00224   volatile avr32_pm_t* pm = &AVR32_PM;
00225   
00226   
00227   // By default, the main clock source is the slow clock. Switch the main clock
00228   // source to be OSC0:
00229   // - Configure OSC0
00230   // - Set the main clock to use OSC0 as input
00231   local_switch_to_osc0(pm);
00232   // From now on, the CPU frequency is FOSC0 Hz.
00233   
00234   // - Configure a generic clock GCLK to use OSC0 as input
00235   // - Output that generic clock to a pin
00236   local_enable_gclk_on_gpio(pm);
00237 
00238   //*** Sleep mode
00239   // If there is a chance that any PB write operations are incomplete, the CPU
00240   // should perform a read operation from any register on the PB bus before
00241   // executing the sleep instruction.
00242   AVR32_INTC.ipr[0];  // Dummy read
00243 
00244   // - Go into a sleep mode (while still maintaining GCLK output)
00245   SLEEP(AVR32_PM_SMODE_FROZEN);
00246 
00247   while(1);
00248 }


Generated on Thu Dec 17 19:58:59 2009 for AVR32 UC3 - Power Manager Driver Example 1 by  doxygen 1.5.5