pm.h File Reference


Detailed Description

Power Manager driver.

Author:
Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file pm.h.

#include <avr32/io.h>
#include "compiler.h"
#include "preprocessor.h"

Go to the source code of this file.

Data Structures

struct  pm_freq_param_t
 Input and output parameters when initializing PM clocks using pm_configure_clocks(). More...

Defines

#define PM_FREQ_STATUS_FAIL   (-1)
#define PM_FREQ_STATUS_OK   (0)
#define SLEEP(mode)   {__asm__ __volatile__ ("sleep "STRINGZ(mode));}
 Sets the MCU in the specified sleep mode.

Functions

void pm_bod_clear_irq (volatile avr32_pm_t *pm)
 Clears the Brown-Out Detector interrupt flag.
void pm_bod_disable_irq (volatile avr32_pm_t *pm)
 Disables the Brown-Out Detector interrupt.
void pm_bod_enable_irq (volatile avr32_pm_t *pm)
 Enables the Brown-Out Detector interrupt.
unsigned long pm_bod_get_irq_enable_bit (volatile avr32_pm_t *pm)
 Gets the Brown-Out Detector interrupt enable status.
unsigned long pm_bod_get_irq_status (volatile avr32_pm_t *pm)
 Gets the Brown-Out Detector interrupt flag.
unsigned long pm_bod_get_level (volatile avr32_pm_t *pm)
 Gets the triggering threshold of the Brown-Out Detector.
void pm_cksel (volatile avr32_pm_t *pm, unsigned int pbadiv, unsigned int pbasel, unsigned int pbbdiv, unsigned int pbbsel, unsigned int hsbdiv, unsigned int hsbsel)
 This function will select all the power manager clocks.
int pm_configure_clocks (pm_freq_param_t *param)
 Automatically configure the CPU, PBA, PBB, and HSB clocks according to the user wishes.
void pm_configure_usb_clock (void)
 Automatically configure the USB clock.
void pm_disable_clk0 (volatile avr32_pm_t *pm)
 This function will disable the oscillator 0.
void pm_disable_clk1 (volatile avr32_pm_t *pm)
 This function will disable the oscillator 1.
void pm_disable_clk32 (volatile avr32_pm_t *pm)
 This function will disable the oscillator 32.
long pm_disable_module (volatile avr32_pm_t *pm, unsigned long module)
 Disable the clock of a module.
void pm_enable_clk0 (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 0 to be used with a startup time.
void pm_enable_clk0_no_wait (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 0 to be used with no startup time.
void pm_enable_clk1 (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 1 to be used with a startup time.
void pm_enable_clk1_no_wait (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 1 to be used with no startup time.
void pm_enable_clk32 (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 32 to be used with a startup time.
void pm_enable_clk32_no_wait (volatile avr32_pm_t *pm, unsigned int startup)
 This function will enable the oscillator 32 to be used with no startup time.
long pm_enable_module (volatile avr32_pm_t *pm, unsigned long module)
 Enable the clock of a module.
void pm_enable_osc0_crystal (volatile avr32_pm_t *pm, unsigned int fosc0)
 This function will enable the crystal mode of the oscillator 0.
void pm_enable_osc0_ext_clock (volatile avr32_pm_t *pm)
 This function will enable the external clock mode of the oscillator 0.
void pm_enable_osc1_crystal (volatile avr32_pm_t *pm, unsigned int fosc1)
 This function will enable the crystal mode of the oscillator 1.
void pm_enable_osc1_ext_clock (volatile avr32_pm_t *pm)
 This function will enable the external clock mode of the oscillator 1.
void pm_enable_osc32_crystal (volatile avr32_pm_t *pm)
 This function will enable the crystal mode of the 32-kHz oscillator.
void pm_enable_osc32_ext_clock (volatile avr32_pm_t *pm)
 This function will enable the external clock mode of the 32-kHz oscillator.
void pm_gc_disable (volatile avr32_pm_t *pm, unsigned int gc)
 This function will disable a generic clock.
void pm_gc_enable (volatile avr32_pm_t *pm, unsigned int gc)
 This function will enable a generic clock.
void pm_gc_setup (volatile avr32_pm_t *pm, unsigned int gc, unsigned int osc_or_pll, unsigned int pll_osc, unsigned int diven, unsigned int div)
 This function will setup a generic clock.
__inline__ unsigned int pm_get_reset_cause (volatile avr32_pm_t *pm)
 Gets the MCU reset cause.
void pm_pll_disable (volatile avr32_pm_t *pm, unsigned int pll)
 This function will disable a PLL.
void pm_pll_enable (volatile avr32_pm_t *pm, unsigned int pll)
 This function will enable a PLL.
unsigned int pm_pll_get_option (volatile avr32_pm_t *pm, unsigned int pll)
 This function will get a PLL option.
void pm_pll_set_option (volatile avr32_pm_t *pm, unsigned int pll, unsigned int pll_freq, unsigned int pll_div2, unsigned int pll_wbwdisable)
 This function will set a PLL option.
void pm_pll_setup (volatile avr32_pm_t *pm, unsigned int pll, unsigned int mul, unsigned int div, unsigned int osc, unsigned int lockcount)
 This function will setup a PLL.
unsigned long pm_read_gplp (volatile avr32_pm_t *pm, unsigned long gplp)
 Read the content of the PM GPLP registers.
void pm_switch_to_clock (volatile avr32_pm_t *pm, unsigned long clock)
 This function will switch the power manager main clock.
void pm_switch_to_osc0 (volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
 Switch main clock to clock Osc0 (crystal mode).
void pm_wait_for_clk0_ready (volatile avr32_pm_t *pm)
 This function will wait until the Osc0 clock is ready.
void pm_wait_for_clk1_ready (volatile avr32_pm_t *pm)
 This function will wait until the Osc1 clock is ready.
void pm_wait_for_clk32_ready (volatile avr32_pm_t *pm)
 This function will wait until the osc32 clock is ready.
void pm_wait_for_pll0_locked (volatile avr32_pm_t *pm)
 This function will wait for PLL0 locked.
void pm_wait_for_pll1_locked (volatile avr32_pm_t *pm)
 This function will wait for PLL1 locked.
void pm_write_gplp (volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value)
 Write into the PM GPLP registers.


Define Documentation

#define PM_FREQ_STATUS_FAIL   (-1)

Definition at line 84 of file pm.h.

Referenced by pm_configure_clocks().

#define PM_FREQ_STATUS_OK   (0)

Definition at line 85 of file pm.h.

Referenced by pm_configure_clocks().

#define SLEEP ( mode   )     {__asm__ __volatile__ ("sleep "STRINGZ(mode));}

Sets the MCU in the specified sleep mode.

Parameters:
mode Sleep mode:
  • AVR32_PM_SMODE_IDLE: Idle;
  • AVR32_PM_SMODE_FROZEN: Frozen;
  • AVR32_PM_SMODE_STANDBY: Standby;
  • AVR32_PM_SMODE_STOP: Stop;
  • AVR32_PM_SMODE_DEEP_STOP: DeepStop;
  • AVR32_PM_SMODE_STATIC: Static.

Definition at line 65 of file pm.h.


Function Documentation

void pm_bod_clear_irq ( volatile avr32_pm_t *  pm  ) 

Clears the Brown-Out Detector interrupt flag.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).

Definition at line 484 of file pm.c.

00485 {
00486   pm->icr = AVR32_PM_ICR_BODDET_MASK;
00487 }

void pm_bod_disable_irq ( volatile avr32_pm_t *  pm  ) 

Disables the Brown-Out Detector interrupt.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).

Definition at line 473 of file pm.c.

00474 {
00475   Bool global_interrupt_enabled = Is_global_interrupt_enabled();
00476 
00477   if (global_interrupt_enabled) Disable_global_interrupt();
00478   pm->idr = AVR32_PM_IDR_BODDET_MASK;
00479   pm->isr;
00480   if (global_interrupt_enabled) Enable_global_interrupt();
00481 }

void pm_bod_enable_irq ( volatile avr32_pm_t *  pm  ) 

Enables the Brown-Out Detector interrupt.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).

Definition at line 467 of file pm.c.

00468 {
00469   pm->ier = AVR32_PM_IER_BODDET_MASK;
00470 }

unsigned long pm_bod_get_irq_enable_bit ( volatile avr32_pm_t *  pm  ) 

Gets the Brown-Out Detector interrupt enable status.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).
Return values:
0 BOD interrupt disabled.
1 BOD interrupt enabled.

Definition at line 496 of file pm.c.

00497 {
00498   return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
00499 }

unsigned long pm_bod_get_irq_status ( volatile avr32_pm_t *  pm  ) 

Gets the Brown-Out Detector interrupt flag.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).
Return values:
0 No BOD interrupt.
1 BOD interrupt pending.

Definition at line 490 of file pm.c.

00491 {
00492   return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
00493 }

unsigned long pm_bod_get_level ( volatile avr32_pm_t *  pm  ) 

Gets the triggering threshold of the Brown-Out Detector.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM).
Returns:
Triggering threshold of the BOD. See the electrical characteristics in the part datasheet for actual voltage levels.

Definition at line 502 of file pm.c.

00503 {
00504   return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
00505 }

void pm_cksel ( volatile avr32_pm_t *  pm,
unsigned int  pbadiv,
unsigned int  pbasel,
unsigned int  pbbdiv,
unsigned int  pbbsel,
unsigned int  hsbdiv,
unsigned int  hsbsel 
)

This function will select all the power manager clocks.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pbadiv Peripheral Bus A clock divisor enable
pbasel Peripheral Bus A select
pbbdiv Peripheral Bus B clock divisor enable
pbbsel Peripheral Bus B select
hsbdiv High Speed Bus clock divisor enable (CPU clock = HSB clock)
hsbsel High Speed Bus select (CPU clock = HSB clock )

Definition at line 327 of file pm.c.

References u_avr32_pm_cksel_t::cksel, and u_avr32_pm_cksel_t::CKSEL.

Referenced by local_start_highfreq_clock(), and pm_configure_clocks().

00334 {
00335   u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
00336 
00337   u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
00338   u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
00339   u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
00340   u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
00341   u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
00342   u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
00343   u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
00344   u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
00345 
00346   pm->cksel = u_avr32_pm_cksel.cksel;
00347 
00348   // Wait for ckrdy bit and then clear it
00349   while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
00350 }

int pm_configure_clocks ( pm_freq_param_t param  ) 

Automatically configure the CPU, PBA, PBB, and HSB clocks according to the user wishes.

This function needs some parameters stored in a pm_freq_param_t structure:

  • cpu_f and pba_f are the wanted frequencies,
  • osc0_f is the oscillator 0 on-board frequency (e.g. FOSC0),
  • osc0_startup is the oscillator 0 startup time (e.g. OSC0_STARTUP).

The function will then configure the clocks using the following rules:

  • It first try to find a valid PLL frequency (the highest possible value to avoid jitter) in order to satisfy the CPU frequency,
  • It optimizes the configuration depending the various divide stages,
  • Then, the PBA frequency is configured from the CPU freq.
  • Note that HSB and PBB are configured with the same frequency as CPU.
  • Note also that the number of wait states of the flash read accesses is automatically set-up depending the CPU frequency. As a consequence, the application needs the FLASHC driver to compile.

The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.

Parameters:
param pointer on the configuration structure.
Return values:
PM_FREQ_STATUS_OK Mode successfully initialized.
PM_FREQ_STATUS_FAIL The configuration can not be done.

Definition at line 61 of file pm_conf_clocks.c.

References pm_freq_param_t::cpu_f, flashc_set_wait_state(), pm_freq_param_t::osc0_f, pm_freq_param_t::osc0_startup, pm_freq_param_t::pba_f, pm_cksel(), PM_FREQ_STATUS_FAIL, PM_FREQ_STATUS_OK, PM_MAX_MUL, pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), pm_switch_to_clock(), pm_switch_to_osc0(), and pm_wait_for_pll0_locked().

Referenced by pcl_configure_clocks().

00062 {
00063   // Supported frequencies:
00064   // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment
00065   //  12   15   1  192     1     12    12
00066   //  12    9   3   40     1     20    20    PLL out of spec
00067   //  12   15   1  192     1     24    12
00068   //  12    9   1  120     1     30    15
00069   //  12    9   3   40     0     40    20    PLL out of spec
00070   //  12   15   1  192     1     48    12
00071   //  12   15   1  192     1     48    24
00072   //  12    8   1  108     1     54    27
00073   //  12    9   1  120     1     60    15
00074   //  12    9   1  120     1     60    30
00075   //  12   10   1  132     1     66    16.5
00076   //
00077   unsigned long in_cpu_f  = param->cpu_f;
00078   unsigned long in_osc0_f = param->osc0_f;
00079   unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
00080   unsigned long pll_freq, rest;
00081   Bool b_div2_pba, b_div2_cpu;
00082 
00083   // Switch to external Oscillator 0
00084   pm_switch_to_osc0(&AVR32_PM, in_osc0_f, param->osc0_startup);
00085 
00086   // Start with CPU freq config
00087   if (in_cpu_f == in_osc0_f)
00088   {
00089     param->cpu_f = in_osc0_f;
00090     param->pba_f = in_osc0_f;
00091     return PM_FREQ_STATUS_OK;
00092   }
00093   else if (in_cpu_f < in_osc0_f)
00094   {
00095     // TBD
00096   }
00097 
00098   rest = in_cpu_f % in_osc0_f;
00099 
00100   for (div = 1; div < 32; div++)
00101   {
00102     if ((div * rest) % in_osc0_f == 0)
00103       break;
00104   }
00105   if (div == 32)
00106     return PM_FREQ_STATUS_FAIL;
00107 
00108   mul = (in_cpu_f * div) / in_osc0_f;
00109 
00110   if (mul > PM_MAX_MUL)
00111     return PM_FREQ_STATUS_FAIL;
00112 
00113   // export 2power from PLL div to div2_cpu
00114   while (!(div % 2))
00115   {
00116     div /= 2;
00117     div2_cpu++;
00118   }
00119 
00120   // Here we know the mul and div parameter of the PLL config.
00121   // . Check out if the PLL has a valid in_cpu_f.
00122   // . Try to have for the PLL frequency (VCO output) the highest possible value
00123   //   to reduce jitter.
00124   while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
00125   {
00126     if (2 * mul > PM_MAX_MUL)
00127       break;
00128     mul *= 2;
00129     div2_cpu++;
00130   }
00131 
00132   if (div2_cpu != 0)
00133   {
00134     div2_cpu--;
00135     div2_en = 1;
00136   }
00137 
00138   pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
00139 
00140   // Update real CPU Frequency
00141   param->cpu_f = pll_freq / (1 << div2_cpu);
00142   mul--;
00143 
00144   pm_pll_setup(&AVR32_PM
00145   , 0   // pll
00146   , mul // mul
00147   , div // div
00148   , 0   // osc
00149   , 16  // lockcount
00150   );
00151 
00152   pm_pll_set_option(&AVR32_PM
00153   , 0 // pll
00154   // PLL clock is lower than 160MHz: need to set pllopt.
00155   , (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0 // pll_freq
00156   , div2_en // pll_div2
00157   , 0 // pll_wbwdisable
00158   );
00159 
00160   rest = pll_freq;
00161   while (rest > AVR32_PM_PBA_MAX_FREQ ||
00162          rest != param->pba_f)
00163   {
00164     div2_pba++;
00165     rest = pll_freq / (1 << div2_pba);
00166     if (rest < param->pba_f)
00167       break;
00168   }
00169 
00170   // Update real PBA Frequency
00171   param->pba_f = pll_freq / (1 << div2_pba);
00172 
00173   // Enable PLL0
00174   pm_pll_enable(&AVR32_PM, 0);
00175 
00176   // Wait for PLL0 locked
00177   pm_wait_for_pll0_locked(&AVR32_PM);
00178 
00179   if (div2_cpu)
00180   {
00181     b_div2_cpu = TRUE;
00182     div2_cpu--;
00183   }
00184   else
00185     b_div2_cpu = FALSE;
00186 
00187   if (div2_pba)
00188   {
00189     b_div2_pba = TRUE;
00190     div2_pba--;
00191   }
00192   else
00193     b_div2_pba = FALSE;
00194 
00195   pm_cksel(&AVR32_PM
00196   , b_div2_pba, div2_pba // PBA
00197   , b_div2_cpu, div2_cpu // PBB
00198   , b_div2_cpu, div2_cpu // HSB
00199   );
00200 
00201   if (param->cpu_f > AVR32_FLASHC_FWS_0_MAX_FREQ)
00202   {
00203     flashc_set_wait_state(1);
00204 #if (defined AVR32_FLASHC_210_H_INCLUDED)
00205     if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
00206       flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
00207     else
00208       flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
00209 #endif
00210   }
00211   else
00212   {
00213     flashc_set_wait_state(0);
00214 #if (defined AVR32_FLASHC_210_H_INCLUDED)
00215     if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
00216       flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
00217     else
00218       flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
00219 #endif
00220   }
00221 
00222   pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
00223 
00224   return PM_FREQ_STATUS_OK;
00225 }

void pm_configure_usb_clock ( void   ) 

Automatically configure the USB clock.

USB clock is configured to 48MHz, using the PLL1 from the Oscillator0, assuming a 12 MHz crystal is connected to it.

Definition at line 228 of file pm_conf_clocks.c.

References pm_gc_enable(), pm_gc_setup(), pm_pll_enable(), pm_pll_set_option(), pm_pll_setup(), and pm_wait_for_pll1_locked().

Referenced by pcl_configure_usb_clock().

00229 {
00230 #if (defined __AVR32_UC3A3256__)  || (defined __AVR32_UC3A3128__)  || (defined __AVR32_UC3A364__)  || \
00231     (defined __AVR32_UC3A3256S__) || (defined __AVR32_UC3A3128S__) || (defined __AVR32_UC3A364S__) || \
00232     (defined __AT32UC3A3256__)  || (defined __AT32UC3A3128__)  || (defined __AT32UC3A364__) ||        \
00233     (defined __AT32UC3A3256S__) || (defined __AT32UC3A3128S__) || (defined __AT32UC3A364S__)
00234 
00235   // Setup USB GCLK.
00236   pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB, // gc
00237                   0,                  // osc_or_pll: use Osc (if 0) or PLL (if 1)
00238                   0,                  // pll_osc: select Osc0/PLL0 or Osc1/PLL1
00239                   0,                  // diven
00240                   0);                 // div
00241 
00242   // Enable USB GCLK.
00243   pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
00244 #else
00245   // Use 12MHz from OSC0 and generate 96 MHz
00246   pm_pll_setup(&AVR32_PM, 1,  // pll.
00247       7,   // mul.
00248       1,   // div.
00249       0,   // osc.
00250       16); // lockcount.
00251 
00252   pm_pll_set_option(&AVR32_PM, 1, // pll.
00253       1,  // pll_freq: choose the range 80-180MHz.
00254       1,  // pll_div2.
00255       0); // pll_wbwdisable.
00256 
00257   // start PLL1 and wait forl lock
00258   pm_pll_enable(&AVR32_PM, 1);
00259 
00260   // Wait for PLL1 locked.
00261   pm_wait_for_pll1_locked(&AVR32_PM);
00262 
00263   pm_gc_setup(&AVR32_PM, AVR32_PM_GCLK_USBB,  // gc.
00264             1,  // osc_or_pll: use Osc (if 0) or PLL (if 1).
00265             1,  // pll_osc: select Osc0/PLL0 or Osc1/PLL1.
00266             0,  // diven.
00267             0); // div.
00268   pm_gc_enable(&AVR32_PM, AVR32_PM_GCLK_USBB);
00269 #endif
00270 }

void pm_disable_clk0 ( volatile avr32_pm_t *  pm  ) 

This function will disable the oscillator 0.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 180 of file pm.c.

00181 {
00182   pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
00183 }

void pm_disable_clk1 ( volatile avr32_pm_t *  pm  ) 

This function will disable the oscillator 1.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 243 of file pm.c.

00244 {
00245   pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
00246 }

void pm_disable_clk32 ( volatile avr32_pm_t *  pm  ) 

This function will disable the oscillator 32.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 303 of file pm.c.

00304 {
00305   pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
00306 }

long pm_disable_module ( volatile avr32_pm_t *  pm,
unsigned long  module 
)

Disable the clock of a module.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
module The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 533 of file pm.c.

00534 {
00535   unsigned long domain = module>>5;
00536   unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain*sizeof(unsigned long));
00537 
00538   // Implementation-specific shortcut: the ckMASK registers are contiguous and
00539   // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
00540 
00541   *regptr &= ~(module%32);
00542 
00543   return PASS;
00544 }

void pm_enable_clk0 ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 0 to be used with a startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.

Definition at line 173 of file pm.c.

References pm_enable_clk0_no_wait(), and pm_wait_for_clk0_ready().

Referenced by pm_switch_to_osc0().

00174 {
00175   pm_enable_clk0_no_wait(pm, startup);
00176   pm_wait_for_clk0_ready(pm);
00177 }

void pm_enable_clk0_no_wait ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 0 to be used with no startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 0 startup time, for which the function does not wait. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.

Definition at line 186 of file pm.c.

References u_avr32_pm_oscctrl0_t::oscctrl0, and u_avr32_pm_oscctrl0_t::OSCCTRL0.

Referenced by pm_enable_clk0().

00187 {
00188   // Read register
00189   u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
00190   // Modify
00191   u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
00192   // Write back
00193   pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
00194 
00195   pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
00196 }

void pm_enable_clk1 ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 1 to be used with a startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 1 startup time. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.

Definition at line 236 of file pm.c.

References pm_enable_clk1_no_wait(), and pm_wait_for_clk1_ready().

00237 {
00238   pm_enable_clk1_no_wait(pm, startup);
00239   pm_wait_for_clk1_ready(pm);
00240 }

void pm_enable_clk1_no_wait ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 1 to be used with no startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 1 startup time, for which the function does not wait. AVR32_PM_OSCCTRL1_STARTUP_x_RCOSC.

Definition at line 249 of file pm.c.

References u_avr32_pm_oscctrl1_t::oscctrl1, and u_avr32_pm_oscctrl1_t::OSCCTRL1.

Referenced by pm_enable_clk1().

00250 {
00251   // Read register
00252   u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
00253   // Modify
00254   u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
00255   // Write back
00256   pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
00257 
00258   pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
00259 }

void pm_enable_clk32 ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 32 to be used with a startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 32 kHz startup time. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.

Definition at line 296 of file pm.c.

References pm_enable_clk32_no_wait(), and pm_wait_for_clk32_ready().

00297 {
00298   pm_enable_clk32_no_wait(pm, startup);
00299   pm_wait_for_clk32_ready(pm);
00300 }

void pm_enable_clk32_no_wait ( volatile avr32_pm_t *  pm,
unsigned int  startup 
)

This function will enable the oscillator 32 to be used with no startup time.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
startup Clock 32 kHz startup time, for which the function does not wait. AVR32_PM_OSCCTRL32_STARTUP_x_RCOSC.

Definition at line 309 of file pm.c.

References u_avr32_pm_oscctrl32_t::oscctrl32, and u_avr32_pm_oscctrl32_t::OSCCTRL32.

Referenced by pm_enable_clk32().

00310 {
00311   // Read register
00312   u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
00313   // Modify
00314   u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
00315   u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
00316   // Write back
00317   pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
00318 }

long pm_enable_module ( volatile avr32_pm_t *  pm,
unsigned long  module 
)

Enable the clock of a module.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
module The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")
Returns:
Status.
Return values:
0 Success.
<0 An error occured.

Definition at line 520 of file pm.c.

00521 {
00522   unsigned long domain = module>>5;
00523   unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain*sizeof(unsigned long));
00524 
00525   // Implementation-specific shortcut: the ckMASK registers are contiguous and
00526   // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
00527 
00528   *regptr |= (module%32);
00529 
00530   return PASS;
00531 }

void pm_enable_osc0_crystal ( volatile avr32_pm_t *  pm,
unsigned int  fosc0 
)

This function will enable the crystal mode of the oscillator 0.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
fosc0 Oscillator 0 crystal frequency (Hz)

Definition at line 164 of file pm.c.

References pm_set_osc0_mode().

Referenced by pm_switch_to_osc0().

00165 {
00166   pm_set_osc0_mode(pm, (fosc0 <  900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 :
00167                        (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 :
00168                        (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
00169                                            AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
00170 }

void pm_enable_osc0_ext_clock ( volatile avr32_pm_t *  pm  ) 

This function will enable the external clock mode of the oscillator 0.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 158 of file pm.c.

References pm_set_osc0_mode().

00159 {
00160   pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
00161 }

void pm_enable_osc1_crystal ( volatile avr32_pm_t *  pm,
unsigned int  fosc1 
)

This function will enable the crystal mode of the oscillator 1.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
fosc1 Oscillator 1 crystal frequency (Hz)

Definition at line 227 of file pm.c.

References pm_set_osc1_mode().

00228 {
00229   pm_set_osc1_mode(pm, (fosc1 <  900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 :
00230                        (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 :
00231                        (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
00232                                            AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
00233 }

void pm_enable_osc1_ext_clock ( volatile avr32_pm_t *  pm  ) 

This function will enable the external clock mode of the oscillator 1.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 221 of file pm.c.

References pm_set_osc1_mode().

00222 {
00223   pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
00224 }

void pm_enable_osc32_crystal ( volatile avr32_pm_t *  pm  ) 

This function will enable the crystal mode of the 32-kHz oscillator.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 290 of file pm.c.

References pm_set_osc32_mode().

00291 {
00292   pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
00293 }

void pm_enable_osc32_ext_clock ( volatile avr32_pm_t *  pm  ) 

This function will enable the external clock mode of the 32-kHz oscillator.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 284 of file pm.c.

References pm_set_osc32_mode().

00285 {
00286   pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
00287 }

void pm_gc_disable ( volatile avr32_pm_t *  pm,
unsigned int  gc 
)

This function will disable a generic clock.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
gc generic clock number (0 for gc0...)

Definition at line 378 of file pm.c.

00380 {
00381   pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
00382 }

void pm_gc_enable ( volatile avr32_pm_t *  pm,
unsigned int  gc 
)

This function will enable a generic clock.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
gc generic clock number (0 for gc0...)

Definition at line 371 of file pm.c.

Referenced by local_start_gc(), and pm_configure_usb_clock().

00373 {
00374   pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
00375 }

void pm_gc_setup ( volatile avr32_pm_t *  pm,
unsigned int  gc,
unsigned int  osc_or_pll,
unsigned int  pll_osc,
unsigned int  diven,
unsigned int  div 
)

This function will setup a generic clock.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
gc generic clock number (0 for gc0...)
osc_or_pll Use OSC (=0) or PLL (=1)
pll_osc Select Osc0/PLL0 or Osc1/PLL1
diven Generic clock divisor enable
div Generic clock divisor

Definition at line 353 of file pm.c.

References u_avr32_pm_gcctrl_t::gcctrl, and u_avr32_pm_gcctrl_t::GCCTRL.

Referenced by local_start_gc(), and pm_configure_usb_clock().

00359 {
00360   u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
00361 
00362   u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
00363   u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
00364   u_avr32_pm_gcctrl.GCCTRL.diven  = diven;
00365   u_avr32_pm_gcctrl.GCCTRL.div    = div;
00366 
00367   pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
00368 }

__inline__ unsigned int pm_get_reset_cause ( volatile avr32_pm_t *  pm  ) 

Gets the MCU reset cause.

Parameters:
pm Base address of the Power Manager instance (i.e. &AVR32_PM).
Returns:
The MCU reset cause which can be masked with the AVR32_PM_RCAUSE_x_MASK bit-masks to isolate specific causes.

Definition at line 98 of file pm.h.

00099 {
00100   return pm->rcause;
00101 }

void pm_pll_disable ( volatile avr32_pm_t *  pm,
unsigned int  pll 
)

This function will disable a PLL.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number(0 for PLL0, 1 for PLL1)

Definition at line 429 of file pm.c.

00431 {
00432   pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
00433 }

void pm_pll_enable ( volatile avr32_pm_t *  pm,
unsigned int  pll 
)

This function will enable a PLL.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number(0 for PLL0, 1 for PLL1)

Definition at line 422 of file pm.c.

Referenced by local_start_highfreq_clock(), pm_configure_clocks(), and pm_configure_usb_clock().

00424 {
00425   pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
00426 }

unsigned int pm_pll_get_option ( volatile avr32_pm_t *  pm,
unsigned int  pll 
)

This function will get a PLL option.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number(0 for PLL0, 1 for PLL1)
Returns:
Option

Definition at line 415 of file pm.c.

00417 {
00418   return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
00419 }

void pm_pll_set_option ( volatile avr32_pm_t *  pm,
unsigned int  pll,
unsigned int  pll_freq,
unsigned int  pll_div2,
unsigned int  pll_wbwdisable 
)

This function will set a PLL option.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number(0 for PLL0, 1 for PLL1)
pll_freq Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.

Definition at line 403 of file pm.c.

References u_avr32_pm_pll_t::pll, and u_avr32_pm_pll_t::PLL.

Referenced by local_start_highfreq_clock(), pm_configure_clocks(), and pm_configure_usb_clock().

00408 {
00409   u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
00410   u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
00411   pm->pll[pll] = u_avr32_pm_pll.pll;
00412 }

void pm_pll_setup ( volatile avr32_pm_t *  pm,
unsigned int  pll,
unsigned int  mul,
unsigned int  div,
unsigned int  osc,
unsigned int  lockcount 
)

This function will setup a PLL.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
pll PLL number(0 for PLL0, 1 for PLL1)
mul PLL MUL in the PLL formula
div PLL DIV in the PLL formula
osc OSC number (0 for osc0, 1 for osc1)
lockcount PLL lockount

Definition at line 385 of file pm.c.

References u_avr32_pm_pll_t::pll, and u_avr32_pm_pll_t::PLL.

Referenced by local_start_highfreq_clock(), pm_configure_clocks(), and pm_configure_usb_clock().

00391 {
00392   u_avr32_pm_pll_t u_avr32_pm_pll = {0};
00393 
00394   u_avr32_pm_pll.PLL.pllosc   = osc;
00395   u_avr32_pm_pll.PLL.plldiv   = div;
00396   u_avr32_pm_pll.PLL.pllmul   = mul;
00397   u_avr32_pm_pll.PLL.pllcount = lockcount;
00398 
00399   pm->pll[pll] = u_avr32_pm_pll.pll;
00400 }

unsigned long pm_read_gplp ( volatile avr32_pm_t *  pm,
unsigned long  gplp 
)

Read the content of the PM GPLP registers.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
Returns:
The content of the chosen GPLP register.

Definition at line 508 of file pm.c.

00509 {
00510   return pm->gplp[gplp];
00511 }

void pm_switch_to_clock ( volatile avr32_pm_t *  pm,
unsigned long  clock 
)

This function will switch the power manager main clock.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
clock Clock to be switched on. AVR32_PM_MCSEL_SLOW for RCOsc, AVR32_PM_MCSEL_OSC0 for Osc0, AVR32_PM_MCSEL_PLL0 for PLL0.

Definition at line 448 of file pm.c.

References u_avr32_pm_mcctrl_t::mcctrl, and u_avr32_pm_mcctrl_t::MCCTRL.

Referenced by local_start_highfreq_clock(), pm_configure_clocks(), and pm_switch_to_osc0().

00449 {
00450   // Read
00451   u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
00452   // Modify
00453   u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
00454   // Write back
00455   pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
00456 }

void pm_switch_to_osc0 ( volatile avr32_pm_t *  pm,
unsigned int  fosc0,
unsigned int  startup 
)

Switch main clock to clock Osc0 (crystal mode).

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
fosc0 Oscillator 0 crystal frequency (Hz)
startup Crystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.

Definition at line 459 of file pm.c.

References pm_enable_clk0(), pm_enable_osc0_crystal(), and pm_switch_to_clock().

Referenced by local_start_highfreq_clock(), pcl_switch_to_osc(), and pm_configure_clocks().

00460 {
00461   pm_enable_osc0_crystal(pm, fosc0);            // Enable the Osc0 in crystal mode
00462   pm_enable_clk0(pm, startup);                  // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
00463   pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
00464 }

void pm_wait_for_clk0_ready ( volatile avr32_pm_t *  pm  ) 

This function will wait until the Osc0 clock is ready.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 199 of file pm.c.

Referenced by pm_enable_clk0().

00200 {
00201   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
00202 }

void pm_wait_for_clk1_ready ( volatile avr32_pm_t *  pm  ) 

This function will wait until the Osc1 clock is ready.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 262 of file pm.c.

Referenced by pm_enable_clk1().

00263 {
00264   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
00265 }

void pm_wait_for_clk32_ready ( volatile avr32_pm_t *  pm  ) 

This function will wait until the osc32 clock is ready.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 321 of file pm.c.

Referenced by pm_enable_clk32().

00322 {
00323   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
00324 }

void pm_wait_for_pll0_locked ( volatile avr32_pm_t *  pm  ) 

This function will wait for PLL0 locked.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 436 of file pm.c.

Referenced by local_start_highfreq_clock(), and pm_configure_clocks().

00437 {
00438   while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
00439 }

void pm_wait_for_pll1_locked ( volatile avr32_pm_t *  pm  ) 

This function will wait for PLL1 locked.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)

Definition at line 442 of file pm.c.

Referenced by pm_configure_usb_clock().

00443 {
00444   while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
00445 }

void pm_write_gplp ( volatile avr32_pm_t *  pm,
unsigned long  gplp,
unsigned long  value 
)

Write into the PM GPLP registers.

Parameters:
pm Base address of the Power Manager (i.e. &AVR32_PM)
gplp GPLP register index (0,1,... depending on the number of GPLP registers for a given part)
value Value to write

Definition at line 514 of file pm.c.

00515 {
00516   pm->gplp[gplp] = value;
00517 }


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