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00048 #include "power_clocks_lib.h"
00049
00050
00052 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00053 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00054 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param);
00055 #endif
00056
00057 #if ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00058 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00059 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param);
00060 #endif
00061
00062 long int pcl_configure_clocks(pcl_freq_param_t *param)
00063 {
00064 #ifndef AVR32_PM_VERSION_RESETVALUE
00065
00066 return(pm_configure_clocks(param));
00067 #else
00068 #ifdef AVR32_PM_410_H_INCLUDED
00069
00070 return(pcl_configure_clocks_uc3c(param));
00071 #else
00072
00073 return(pcl_configure_clocks_uc3l(param));
00074 #endif
00075 #endif
00076 }
00077
00078
00080 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00081 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00082
00083 static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
00084 unsigned long main_clock_freq_hz,
00085 pcl_freq_param_t *param);
00086
00087 long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
00088 {
00089
00090
00091
00092
00093
00094
00095
00096
00097 #ifdef AVR32SFW_INPUT_CHECK
00098
00099 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00100 return(-1);
00101 #endif
00102
00103 #ifdef AVR32SFW_INPUT_CHECK
00104
00105 if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
00106 || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
00107 return(-1);
00108 #endif
00109
00110 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
00111 }
00112
00113
00114 long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
00115 {
00116
00117
00118
00119
00120
00121
00122
00123
00124 #ifdef AVR32SFW_INPUT_CHECK
00125
00126 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00127 return(-1);
00128 #endif
00129
00130 #ifdef AVR32SFW_INPUT_CHECK
00131
00132 if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
00133 || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
00134 return(-1);
00135 #endif
00136
00137
00138 scif_start_rc120M();
00139
00140 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
00141 }
00142
00143
00144 long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
00145 {
00146
00147
00148
00149
00150
00151
00152
00153
00154
00155 unsigned long main_clock_freq;
00156
00157
00158 #ifdef AVR32SFW_INPUT_CHECK
00159
00160 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00161 return(-1);
00162 #endif
00163
00164 main_clock_freq = param->osc0_f;
00165 #ifdef AVR32SFW_INPUT_CHECK
00166
00167 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00168 || (param->pbb_f > main_clock_freq))
00169 return(-1);
00170 #endif
00171
00172 scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
00173
00174 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
00175
00176 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
00177 }
00178
00179
00180 long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
00181 {
00182
00183
00184
00185
00186
00187
00188
00189
00190
00191 unsigned long main_clock_freq;
00192 scif_gclk_opt_t *pgc_dfllif_ref_opt;
00193
00194
00195 #ifdef AVR32SFW_INPUT_CHECK
00196
00197 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00198 return(-1);
00199 #endif
00200
00201 main_clock_freq = param->dfll_f;
00202 #ifdef AVR32SFW_INPUT_CHECK
00203
00204 if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
00205 return(-1);
00206
00207 if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00208 || (param->pbb_f > main_clock_freq))
00209 return(-1);
00210 #endif
00211 pgc_dfllif_ref_opt = (scif_gclk_opt_t *)param->pextra_params;
00212
00213
00214
00215 scif_dfll0_closedloop_configure_and_start(pgc_dfllif_ref_opt, main_clock_freq, TRUE);
00216
00217 return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
00218 }
00219
00220
00221 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
00222 {
00223
00224
00225
00226
00227
00228
00229
00230
00231
00232
00233
00234
00235
00236
00237
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00239
00240
00241
00242
00243 #ifdef AVR32SFW_INPUT_CHECK
00244
00245 if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00246 return(-1);
00247 #endif
00248
00249 if(PCL_MC_RCSYS == param->main_clk_src)
00250 {
00251 return(pcl_configure_clocks_rcsys(param));
00252 }
00253 else if(PCL_MC_RC120M == param->main_clk_src)
00254 {
00255 return(pcl_configure_clocks_rc120m(param));
00256 }
00257 else if(PCL_MC_OSC0 == param->main_clk_src)
00258 {
00259 return(pcl_configure_clocks_osc0(param));
00260 }
00261 else
00262 {
00263 return(pcl_configure_clocks_dfll0(param));
00264 }
00265 }
00266
00267 static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
00268 {
00269
00270
00271
00272 pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
00273
00274
00275
00276
00277 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00278 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00279 flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
00280 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00281 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00282 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
00283 #endif
00284
00285
00286
00287
00288
00289 pm_set_mclk_source(main_clk_src);
00290
00291 return PASS;
00292 }
00293
00294 #endif // UC3L device-specific implementation
00295
00297 #if ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00298 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00299 static long int pcl_configure_clocks_uc3c(pcl_freq_param_t *param)
00300 {
00301 #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
00302 #define AVR32_PM_PBA_MAX_FREQ 66000000
00303 #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000
00304 #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000
00305
00306
00307
00308
00309
00310
00311
00312
00313
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00315
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00320
00321 unsigned long in_cpu_f = param->cpu_f;
00322 unsigned long in_osc0_f = param->osc0_f;
00323 unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
00324 unsigned long pll_freq, rest;
00325 Bool b_div2_pba, b_div2_cpu;
00326
00327
00328 scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
00329
00330 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
00331
00332 pm_set_mclk_source(PM_CLK_SRC_OSC0);
00333
00334
00335 if (in_cpu_f == in_osc0_f)
00336 {
00337 param->cpu_f = in_osc0_f;
00338 param->pba_f = in_osc0_f;
00339 return PASS;
00340 }
00341 else if (in_cpu_f < in_osc0_f)
00342 {
00343
00344 }
00345
00346 rest = in_cpu_f % in_osc0_f;
00347
00348 for (div = 1; div < 32; div++)
00349 {
00350 if ((div * rest) % in_osc0_f == 0)
00351 break;
00352 }
00353 if (div == 32)
00354 return FAIL;
00355
00356 mul = (in_cpu_f * div) / in_osc0_f;
00357
00358 if (mul > PM_MAX_MUL)
00359 return FAIL;
00360
00361
00362 while (!(div % 2))
00363 {
00364 div /= 2;
00365 div2_cpu++;
00366 }
00367
00368
00369
00370
00371
00372 while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
00373 {
00374 if (2 * mul > PM_MAX_MUL)
00375 break;
00376 mul *= 2;
00377 div2_cpu++;
00378 }
00379
00380 if (div2_cpu != 0)
00381 {
00382 div2_cpu--;
00383 div2_en = 1;
00384 }
00385
00386 pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
00387
00388
00389 param->cpu_f = pll_freq / (1 << div2_cpu);
00390 mul--;
00391
00392 scif_pll_opt_t opt;
00393
00394 opt.osc = SCIF_OSC0,
00395 opt.lockcount = 16,
00396 opt.div = div,
00397 opt.mul = mul,
00398 opt.pll_div2 = div2_en,
00399 opt.pll_wbwdisable = 0,
00400 opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,
00401
00402
00403 scif_pll_setup(SCIF_PLL0, opt);
00404
00405
00406 scif_pll_enable(SCIF_PLL0);
00407
00408
00409 scif_wait_for_pll_locked(SCIF_PLL0) ;
00410
00411 rest = pll_freq;
00412 while (rest > AVR32_PM_PBA_MAX_FREQ ||
00413 rest != param->pba_f)
00414 {
00415 div2_pba++;
00416 rest = pll_freq / (1 << div2_pba);
00417 if (rest < param->pba_f)
00418 break;
00419 }
00420
00421
00422 param->pba_f = pll_freq / (1 << div2_pba);
00423
00424
00425 if (div2_cpu)
00426 {
00427 b_div2_cpu = TRUE;
00428 div2_cpu--;
00429 }
00430 else
00431 b_div2_cpu = FALSE;
00432
00433 if (div2_pba)
00434 {
00435 b_div2_pba = TRUE;
00436 div2_pba--;
00437 }
00438 else
00439 b_div2_pba = FALSE;
00440
00441 if (b_div2_cpu == TRUE )
00442 {
00443 pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu);
00444 pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu);
00445 pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu);
00446 }
00447 if (b_div2_pba == TRUE )
00448 {
00449 pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba);
00450 pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba);
00451 }
00452
00453
00454 flashc_set_flash_waitstate_and_readmode(param->cpu_f);
00455
00456
00457 pm_set_mclk_source(PM_CLK_SRC_PLL0);
00458
00459 return PASS;
00460 }
00461 #endif // UC3C device-specific implementation
00462
00463 long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
00464 {
00465 #ifndef AVR32_PM_VERSION_RESETVALUE
00466
00467 if(PCL_OSC0 == osc)
00468 {
00469
00470
00471 pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
00472 }
00473 else
00474 {
00475 return PCL_NOT_SUPPORTED;
00476 }
00477 #else
00478
00479 #if AVR32_PM_VERSION_RESETVALUE < 0x400
00480 return PCL_NOT_SUPPORTED;
00481 #else
00482 if(PCL_OSC0 == osc)
00483 {
00484
00485 scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
00486
00487 scif_enable_osc(SCIF_OSC0, startup, true);
00488
00489 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00490 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00491 flashcdw_set_flash_waitstate_and_readmode(fcrystal);
00492 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00493 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00494 flashc_set_flash_waitstate_and_readmode(fcrystal);
00495 #endif
00496
00497 pm_set_mclk_source(PM_CLK_SRC_OSC0);
00498 }
00499 else
00500 {
00501 return PCL_NOT_SUPPORTED;
00502 }
00503 #endif
00504 #endif
00505 return PASS;
00506 }
00507
00508 long int pcl_configure_usb_clock(void)
00509 {
00510 #ifndef AVR32_PM_VERSION_RESETVALUE
00511
00512 pm_configure_usb_clock();
00513 #else
00514 #ifdef AVR32_PM_410_H_INCLUDED
00515 const scif_pll_opt_t opt = {
00516 .osc = SCIF_OSC0,
00517 .lockcount = 16,
00518 .div = 1,
00519 .mul = 5,
00520 .pll_div2 = 1,
00521 .pll_wbwdisable = 0,
00522 .pll_freq = 1,
00523 };
00524
00525
00526 scif_pll_setup(SCIF_PLL1, opt);
00527
00528
00529 scif_pll_enable(SCIF_PLL1);
00530
00531
00532 scif_wait_for_pll_locked(SCIF_PLL1) ;
00533
00534
00535
00536 scif_gc_setup(AVR32_SCIF_GCLK_USB,
00537 SCIF_GCCTRL_PLL1,
00538 AVR32_SCIF_GC_NO_DIV_CLOCK,
00539 0);
00540
00541 scif_gc_enable(AVR32_SCIF_GCLK_USB);
00542 #else
00543 return PCL_NOT_SUPPORTED;
00544 #endif
00545 #endif
00546 return PASS;
00547 }
00548
00549
00550 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00551 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00552 #else
00553 void pcl_write_gplp(unsigned long gplp, unsigned long value)
00554 {
00555 #ifndef AVR32_PM_VERSION_RESETVALUE
00556
00557 pm_write_gplp(&AVR32_PM,gplp,value);
00558 #else
00559 scif_write_gplp(gplp,value);
00560 #endif
00561 }
00562
00563 unsigned long pcl_read_gplp(unsigned long gplp)
00564 {
00565 #ifndef AVR32_PM_VERSION_RESETVALUE
00566
00567 return pm_read_gplp(&AVR32_PM,gplp);
00568 #else
00569 return scif_read_gplp(gplp);
00570 #endif
00571 }
00572 #endif