Definition in file gpio_local_bus_example.c.
#include "compiler.h"
#include "preprocessor.h"
#include "board.h"
#include "power_clocks_lib.h"
#include "gpio.h"
Go to the source code of this file.
Defines | |
#define | INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) gpio_local_tgl_gpio_pin(pin); |
Target DFLL0 frequency | |
#define | EXAMPLE_FDFLL_HZ (100000000ULL) |
#define | EXAMPLE_FDFLL_KHZ (100000UL) |
#define | EXAMPLE_MCUCLK_HZ (25000000UL) |
Pin Configuration | |
#define | GPIO_PIN_EXAMPLE AVR32_PIN_PA10 |
Functions | |
static void | fcpu_fpba_configure () |
int | main (void) |
This is an example showing how to toggle a GPIO pin at high speed. |
#define EXAMPLE_FDFLL_HZ (100000000ULL) |
#define EXAMPLE_FDFLL_KHZ (100000UL) |
Definition at line 137 of file gpio_local_bus_example.c.
#define EXAMPLE_MCUCLK_HZ (25000000UL) |
#define GPIO_PIN_EXAMPLE AVR32_PIN_PA10 |
#define INSERT_GPIO_LOCAL_TGL_GPIO_PIN | ( | idx, | |||
pin | ) | gpio_local_tgl_gpio_pin(pin); |
Referenced by main().
static void fcpu_fpba_configure | ( | ) | [static] |
Definition at line 145 of file gpio_local_bus_example.c.
References EXAMPLE_FDFLL_HZ, and EXAMPLE_MCUCLK_HZ.
Referenced by main().
00146 { 00147 #if ((defined (__GNUC__) && (defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__) )) \ 00148 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) ))) 00149 static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF }; 00150 static pcl_freq_param_t pcl_dfll_freq_param = 00151 { 00152 .main_clk_src = PCL_MC_DFLL0, 00153 .cpu_f = EXAMPLE_MCUCLK_HZ, 00154 .pba_f = EXAMPLE_MCUCLK_HZ, 00155 .pbb_f = EXAMPLE_MCUCLK_HZ, 00156 .dfll_f = EXAMPLE_FDFLL_HZ, 00157 .pextra_params = &gc_dfllif_ref_opt 00158 }; 00159 // Implementation for UC3L 00160 // Note: on the AT32UC3L-EK board, there is no crystal/external clock connected 00161 // to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the 00162 // main clock source to the DFLL. 00163 pcl_configure_clocks(&pcl_dfll_freq_param); 00164 // Note: since it is dynamically computing the appropriate field values of the 00165 // configuration registers from the parameters structure, this function is not 00166 // optimal in terms of code size. For a code size optimal solution, it is better 00167 // to create a new function from pcl_configure_clocks_dfll0() and modify it 00168 // to use preprocessor computation from pre-defined target frequencies. 00169 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \ 00170 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__))) 00171 // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency. 00172 scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0); 00173 // Enable the OSC0 00174 scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true); 00175 // Set the main clock source as being OSC0. 00176 pm_set_mclk_source(PM_CLK_SRC_OSC0); 00177 00178 scif_pll_opt_t opt; 00179 00180 // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output 00181 opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1 00182 opt.lockcount = 16; // lockcount in main clock for the PLL wait lock 00183 opt.div = 1; // DIV=1 in the formula 00184 opt.mul = 7; // MUL=7 in the formula 00185 opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) 00186 opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. 00187 opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. 00188 00189 00190 scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock 00191 00192 /* Enable PLL0 */ 00193 scif_pll_enable(SCIF_PLL0); 00194 00195 /* Wait for PLL0 locked */ 00196 scif_wait_for_pll_locked(SCIF_PLL0) ; 00197 00198 // Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz 00199 pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU 00200 pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB 00201 pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB 00202 pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA 00203 pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC 00204 00205 /* Set the main clock source as being PLL0. */ 00206 pm_set_mclk_source(PM_CLK_SRC_PLL0); 00207 00208 #else 00209 // Switch the main clock source to Osc0. 00210 pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP); 00211 00212 // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output 00213 pm_pll_setup(&AVR32_PM, 0, // pll. 00214 10, // mul. 00215 1, // div. 00216 0, // osc. 00217 16); // lockcount. 00218 // PLL output VCO frequency is 132MHz. 00219 // We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz. 00220 pm_pll_set_option(&AVR32_PM, 0, // pll. 00221 1, // pll_freq. 00222 1, // pll_div2. 00223 0); // pll_wbwdisable. 00224 // Enable the PLL. 00225 pm_pll_enable(&AVR32_PM, 0); 00226 // Wait until the PLL output is stable. 00227 pm_wait_for_pll0_locked(&AVR32_PM); 00228 // Configure each clock domain to use the main clock divided by 2 00229 // => fCPU = fPBA = fPBB = 33MHz. 00230 pm_cksel(&AVR32_PM, 00231 1, // pbadiv. 00232 0, // pbasel. 00233 1, // pbbdiv. 00234 0, // pbbsel. 00235 1, // hsbdiv=cpudiv 00236 0); // hsbsel=cpusel 00237 // Switch the main clock source to PLL0. 00238 pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0); 00239 #endif 00240 }
int main | ( | void | ) |
This is an example showing how to toggle a GPIO pin at high speed.
Definition at line 245 of file gpio_local_bus_example.c.
References fcpu_fpba_configure(), gpio_local_enable_pin_output_driver(), gpio_local_init(), GPIO_PIN_EXAMPLE, and INSERT_GPIO_LOCAL_TGL_GPIO_PIN.
00246 { 00247 // Initialize domain clocks (CPU, HSB, PBA and PBB) to the max frequency available 00248 // without flash wait states. 00249 // Some of the registers in the GPIO module are mapped onto the CPU local bus. 00250 // To ensure maximum transfer speed and cycle determinism, any slaves being 00251 // addressed by the CPU on the local bus must be able to receive and transmit 00252 // data on the bus at CPU clock speeds. The consequences of this is that the 00253 // GPIO module has to run at the CPU clock frequency when local bus transfers 00254 // are being performed => we want fPBA = fCPU. 00255 fcpu_fpba_configure(); 00256 00257 // Enable the local bus interface for GPIO. 00258 gpio_local_init(); 00259 00260 // Enable the output driver of the example pin. 00261 // Note that the GPIO mode of pins is enabled by default after reset. 00262 gpio_local_enable_pin_output_driver(GPIO_PIN_EXAMPLE); 00263 00264 // Toggle the example GPIO pin at high speed in a loop. 00265 while (1) 00266 { 00267 // Explicit loop unrolling allowing consecutive ST.W instructions without 00268 // loop overhead if compiler optimization is activated, except every 128 00269 // ST.W for the while loop. 00270 #define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) \ 00271 gpio_local_tgl_gpio_pin(pin); 00272 MREPEAT(128, INSERT_GPIO_LOCAL_TGL_GPIO_PIN, GPIO_PIN_EXAMPLE) 00273 #undef INSERT_GPIO_LOCAL_TGL_GPIO_PIN 00274 } 00275 }