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00046 #ifndef _PM_UC3L_H_
00047 #define _PM_UC3L_H_
00048
00049 #ifdef __cplusplus
00050 extern "C" {
00051 #endif
00052
00053 #include <avr32/io.h>
00054 #include "compiler.h"
00055
00057 #if ((__GNUC__ && (__AVR32_UC3L016__ || __AVR32_UC3L032__ || __AVR32_UC3L064__)) \
00058 ||(__ICCAVR32__ && (__AT32UC3L016__ || __AT32UC3L032__ || __AT32UC3L064__ )))
00059
00060
00062 typedef enum
00063 {
00064 PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW,
00065 PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0,
00066 PM_CLK_SRC_DFLL0 = AVR32_PM_MCSEL_DFLL0,
00067 PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M,
00068 PM_CLK_SRC_INVALID
00069 } pm_clk_src_t;
00070
00072 typedef enum
00073 {
00074 PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU,
00075 PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB,
00076 PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA,
00077 PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB,
00078 PM_CLK_DOMAIN_INVALID
00079 } pm_clk_domain_t;
00080
00081
00083 typedef enum
00084 {
00085 PM_CKSEL_DIVRATIO_2 = 0,
00086 PM_CKSEL_DIVRATIO_4,
00087 PM_CKSEL_DIVRATIO_8,
00088 PM_CKSEL_DIVRATIO_16,
00089 PM_CKSEL_DIVRATIO_32,
00090 PM_CKSEL_DIVRATIO_64,
00091 PM_CKSEL_DIVRATIO_128,
00092 PM_CKSEL_DIVRATIO_256,
00093 PM_CKSEL_DIVRATIO_ERROR
00094 } pm_divratio_t;
00095
00097 typedef enum
00098 {
00099 PM_CPUSEL_DIVRATIO_MAX = AVR32_PM_CPUSEL_CPUSEL_MASK >> AVR32_PM_CPUSEL_CPUSEL_OFFSET,
00100 PM_HSBSEL_DIVRATIO_MAX = AVR32_PM_HSBSEL_HSBSEL_MASK >> AVR32_PM_HSBSEL_HSBSEL_OFFSET,
00101 PM_PBASEL_DIVRATIO_MAX = AVR32_PM_PBASEL_PBSEL_MASK >> AVR32_PM_PBASEL_PBSEL_OFFSET,
00102 PM_PBBSEL_DIVRATIO_MAX = AVR32_PM_PBBSEL_PBSEL_MASK >> AVR32_PM_PBBSEL_PBSEL_OFFSET
00103 } pm_divratio_max_t;
00104
00105 #endif
00106
00108 #define PM_POLL_TIMEOUT 100000
00109
00111 #define PM_NOT_SUPPORTED (-10000)
00112
00113
00115 #define PM_UNLOCK(reg) (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg))
00116
00117
00120
00121
00133 extern long pm_set_mclk_source(pm_clk_src_t src);
00134
00150 extern long pm_config_mainclk_safety(bool cfd, bool ocp, bool final);
00151
00164 extern long pm_set_clk_domain_div(pm_clk_domain_t clock_domain, pm_divratio_t divratio);
00165
00177 extern long pm_disable_clk_domain_div(pm_clk_domain_t clock_domain);
00178
00191 extern void pm_set_all_cksel( unsigned long main_clock_f_hz, unsigned long cpu_f_hz,
00192 unsigned long pba_f_hz, unsigned long pbb_f_hz );
00193
00203 extern long pm_wait_for_clk_ready(void);
00204
00206
00207
00210
00211
00222 extern long pm_enable_module(unsigned long module);
00223
00234 extern long pm_disable_module(unsigned long module);
00235
00236
00238
00241
00242
00250 #define pm_sleep(sleep_mode) {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));}
00251
00252 #define SLEEP(sleep_mode) pm_sleep(sleep_mode)
00253
00259 #if __GNUC__
00260 __attribute__((__always_inline__))
00261 #endif
00262 extern __inline__ unsigned long pm_get_wake_cause(void)
00263 {
00264 return AVR32_PM.wcause;
00265 }
00266
00273 #if __GNUC__
00274 __attribute__((__always_inline__))
00275 #endif
00276 extern __inline__ void pm_asyn_wake_up_enable(unsigned long awen_mask)
00277 {
00278 AVR32_PM.awen |= awen_mask;
00279 }
00280
00287 #if __GNUC__
00288 __attribute__((__always_inline__))
00289 #endif
00290 extern __inline__ void pm_asyn_wake_up_disable(unsigned long awen_mask)
00291 {
00292 AVR32_PM.awen &= ~awen_mask;
00293 }
00294
00296
00297
00298
00301
00302
00308 #if __GNUC__
00309 __attribute__((__always_inline__))
00310 #endif
00311 extern __inline__ unsigned long pm_get_reset_cause(void)
00312 {
00313 return AVR32_PM.rcause;
00314 }
00315
00317
00318
00319
00322
00323
00329 #if __GNUC__
00330 __attribute__((__always_inline__))
00331 #endif
00332 extern __inline__ void pm_enable_interrupts(unsigned long mask)
00333 {
00334 AVR32_PM.ier |= mask;
00335 }
00336
00342 #if __GNUC__
00343 __attribute__((__always_inline__))
00344 #endif
00345 extern __inline__ void pm_disable_interrupts(unsigned long mask)
00346 {
00347 AVR32_PM.idr |= mask;
00348 }
00349
00354 #if __GNUC__
00355 __attribute__((__always_inline__))
00356 #endif
00357 extern __inline__ unsigned long pm_get_enabled_interrupts(void)
00358 {
00359 return(AVR32_PM.imr);
00360 }
00361
00366 #if __GNUC__
00367 __attribute__((__always_inline__))
00368 #endif
00369 extern __inline__ unsigned long pm_get_interrupts_status(void)
00370 {
00371 return(AVR32_PM.isr);
00372 }
00373
00378 #if __GNUC__
00379 __attribute__((__always_inline__))
00380 #endif
00381 extern __inline__ void pm_clear_interrupt_status(unsigned long mask)
00382 {
00383 AVR32_PM.icr |= mask;
00384 }
00385
00387
00388
00389
00392
00393
00398 #if __GNUC__
00399 __attribute__((__always_inline__))
00400 #endif
00401 extern __inline__ unsigned long pm_get_status(void)
00402 {
00403 return AVR32_PM.sr;
00404 }
00405
00407
00408 #ifdef __cplusplus
00409 }
00410 #endif
00411
00412 #endif // _PM_UC3L_H_