00001
00102 #include "compiler.h"
00103 #include "preprocessor.h"
00104 #include "board.h"
00105 #if ((defined (__GNUC__) && (defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
00106 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00107
00108
00109
00110 #include "power_clocks_lib.h"
00111 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00112 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00113 #include "scif_uc3c.h"
00114 #include "pm_uc3c.h"
00115 #else
00116 #include "pm.h"
00117 #endif
00118 #include "gpio.h"
00119
00120
00121
00122
00123
00126
00127 #define GPIO_PIN_EXAMPLE AVR32_PIN_PA10
00129
00130
00133
00134 #if ((defined (__GNUC__) && (defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__) )) \
00135 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00136 #define EXAMPLE_FDFLL_HZ (100000000ULL) // 100MHz
00137 #define EXAMPLE_FDFLL_KHZ (100000UL)
00138 #define EXAMPLE_MCUCLK_HZ (25000000UL) // 25MHz
00139 #endif
00140
00141
00143
00144
00145 static void fcpu_fpba_configure()
00146 {
00147 #if ((defined (__GNUC__) && (defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__) )) \
00148 ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__) )))
00149 static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF };
00150 static pcl_freq_param_t pcl_dfll_freq_param =
00151 {
00152 .main_clk_src = PCL_MC_DFLL0,
00153 .cpu_f = EXAMPLE_MCUCLK_HZ,
00154 .pba_f = EXAMPLE_MCUCLK_HZ,
00155 .pbb_f = EXAMPLE_MCUCLK_HZ,
00156 .dfll_f = EXAMPLE_FDFLL_HZ,
00157 .pextra_params = &gc_dfllif_ref_opt
00158 };
00159
00160
00161
00162
00163 pcl_configure_clocks(&pcl_dfll_freq_param);
00164
00165
00166
00167
00168
00169 #elif ( defined (__GNUC__) && ( defined (__AVR32_UC3C064C__) || defined (__AVR32_UC3C0128C__) || defined (__AVR32_UC3C0256C__) || defined (__AVR32_UC3C0512CREVC__) || defined (__AVR32_UC3C164C__) || defined (__AVR32_UC3C1128C__) || defined (__AVR32_UC3C1256C__) || defined (__AVR32_UC3C1512CREVC__) || defined (__AVR32_UC3C264C__) || defined (__AVR32_UC3C2128C__) || defined (__AVR32_UC3C2256C__) || defined (__AVR32_UC3C2512CREVC__))) \
00170 ||( defined (__ICCAVR32__) && ( defined (__AT32UC3C064C__) || defined (__AT32UC3C0128C__) || defined (__AT32UC3C0256C__) || defined (__AT32UC3C0512C__) || defined (__AT32UC3C164C__) || defined (__AT32UC3C1128C__) || defined (__AT32UC3C1256C__) || defined (__AT32UC3C1512C__) || defined (__AT32UC3C264C__) || defined (__AT32UC3C2128C__) || defined (__AT32UC3C2256C__) || defined (__AT32UC3C2512C__)))
00171
00172 scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
00173
00174 scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
00175
00176 pm_set_mclk_source(PM_CLK_SRC_OSC0);
00177
00178 scif_pll_opt_t opt;
00179
00180
00181 opt.osc = SCIF_OSC0;
00182 opt.lockcount = 16;
00183 opt.div = 1;
00184 opt.mul = 7;
00185 opt.pll_div2 = 1;
00186 opt.pll_wbwdisable = 0;
00187 opt.pll_freq = 1;
00188
00189
00190 scif_pll_setup(SCIF_PLL0, opt);
00191
00192
00193 scif_pll_enable(SCIF_PLL0);
00194
00195
00196 scif_wait_for_pll_locked(SCIF_PLL0) ;
00197
00198
00199 pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0);
00200 pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0);
00201 pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0);
00202 pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0);
00203 pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0);
00204
00205
00206 pm_set_mclk_source(PM_CLK_SRC_PLL0);
00207
00208 #else
00209
00210 pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
00211
00212
00213 pm_pll_setup(&AVR32_PM, 0,
00214 10,
00215 1,
00216 0,
00217 16);
00218
00219
00220 pm_pll_set_option(&AVR32_PM, 0,
00221 1,
00222 1,
00223 0);
00224
00225 pm_pll_enable(&AVR32_PM, 0);
00226
00227 pm_wait_for_pll0_locked(&AVR32_PM);
00228
00229
00230 pm_cksel(&AVR32_PM,
00231 1,
00232 0,
00233 1,
00234 0,
00235 1,
00236 0);
00237
00238 pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
00239 #endif
00240 }
00241
00242
00245 int main(void)
00246 {
00247
00248
00249
00250
00251
00252
00253
00254
00255 fcpu_fpba_configure();
00256
00257
00258 gpio_local_init();
00259
00260
00261
00262 gpio_local_enable_pin_output_driver(GPIO_PIN_EXAMPLE);
00263
00264
00265 while (1)
00266 {
00267
00268
00269
00270 #define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) \
00271 gpio_local_tgl_gpio_pin(pin);
00272 MREPEAT(128, INSERT_GPIO_LOCAL_TGL_GPIO_PIN, GPIO_PIN_EXAMPLE)
00273 #undef INSERT_GPIO_LOCAL_TGL_GPIO_PIN
00274 }
00275 }