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RE: [openrisc] Cell not translated
Hmm, never used the command line.
RAMb4_16 is a Xilinx primitive, I don't know if there's a verilog file
called like that. There's a directory containing a bunch of xilinx
prepared functions. See if it contains RAMB4_16.v and included that
directory.
Maybe that helps.
Richard
> -----Original Message-----
> From: [email protected]
> [mailto:[email protected]] On Behalf Of [email protected]
> Sent: vrijdag 8 augustus 2003 8:30
> To: [email protected]; [email protected]
> Subject: Re: [openrisc] Cell not translated
>
>
> Hello Richard,
> I am using Xilinx ISE to synthesize or1200. I
> have written a
> script file to synthesize it. Problem here is that, at the
> xst prompt, when
> it is analyzing, it reads RAMB4_16.v library and fails. The error msg
> is "Unsupported tri0 net type". Did you get the same msg when
> you tried
> to synthesize?
> This is the first time I am trying to synthesize using Xilinx
> ISE. If there is
> a more efficient way to do it please let me know. I have been
> comfortable with scripts, so I was trying that out.
> Please help!
>
> Regards,
> Sandeep.
>
> ----- Original Message -----
> From: Richard Herveille <richard@a... >
> To: openrisc@o...
> Date: Sat, 15 Feb 2003 10:02:21 +0100
> Subject: Re: [openrisc] Cell not translated
>
> >
> >
> >
> > This is a synthesizer warning that it cannot instantiate the
> > ramblocks.
> > Apparantly OpenRISC is currently configured for Xilinx memories.
> > Replace the
> > blocks with your FPGA vendor's equivalent of Xilinx' RAMB4_16.
> > Altera for
> > example has direct replacements for them.
> > And yes OR1200 is synthesizable, it's running on my board.
> >
> > Richard
> >
> >
> > > Hi, All,
> > >
> > > I want to use OpenRisc as the netlist for my project. When I
> > try to compile
> > > and synthsis, there is warning:
> > >
> > > Warning: Cell
> > 'or1200_immu_top/or1200_immu_tlb/itlb_mr_ram/ramb4_s16_0'
> > > (RAMB4_S16) not translated. (TRANS-1) Warning: Cell
> > > 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_0'
> > (RAMB4_S16_1) not
> > > translated. (TRANS-1) Warning: Cell
> > > 'or1200_immu_top/or1200_immu_tlb/itlb_tr_ram/ramb4_s16_1'
> > > (RAMB4_S16_param_1) not translated. (TRANS-1) Warning: Cell
> > > 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_0' (RAMB4_S4)
> > not translated.
> > > (TRANS-1) Warning: Cell
> > 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_1'
> > > (RAMB4_S4_param_1) not translated. (TRANS-1) Warning: Cell
> > > 'or1200_ic_top/or1200_ic_ram/ic_ram0/ramb4_s4_2'
> > (RAMB4_S4_param_2) not
> > > translated. ......
> > >
> > > Anyone can tell me why and how to make it synthsizable?
> > >
> > > Is OpenRisc1200 synthsizable?
> > >
> > > Thanks in advance.
> > >
> > > Lei
> >
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