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-- VHDL structural description generated from `dffres`
-- date : Wed Jan 10 18:51:06 2001
-- Entity Declaration
ENTITY dffres IS
PORT (
input : in BIT; -- input
clk : in BIT; -- clk
reset : in BIT; -- reset
output : out BIT; -- output
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END dffres;
-- Architecture Declaration
ARCHITECTURE VST OF dffres IS
COMPONENT inv_x1
port (
i : in BIT; -- i
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT o2_x2
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT no2_x1
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
nq : out BIT; -- nq
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT sff1_x4
port (
ck : in BIT; -- ck
i : in BIT; -- i
q : out BIT; -- q
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL auxsc3 : BIT; -- auxsc3
SIGNAL auxsc4 : BIT; -- auxsc4
SIGNAL auxreg1 : BIT; -- auxreg1
BEGIN
output : inv_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => output,
i => auxreg1);
auxsc4 : o2_x2
PORT MAP (
vss => vss,
vdd => vdd,
q => auxsc4,
i1 => auxsc3,
i0 => reset);
auxsc3 : no2_x1
PORT MAP (
vss => vss,
vdd => vdd,
nq => auxsc3,
i1 => input,
i0 => reset);
dffres_reg : sff1_x4
PORT MAP (
vss => vss,
vdd => vdd,
q => auxreg1,
i => auxsc4,
ck => clk);
end VST;
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