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-- VHDL structural description generated from `counter`
-- date : Tue Feb 20 14:23:43 2001
-- Entity Declaration
ENTITY counter IS
PORT (
e : in BIT; -- e
ck : in BIT; -- ck
res : in BIT; -- res
vdd : in BIT; -- vdd
vss : in BIT; -- vss
a : out BIT_VECTOR (0 TO 4); -- a
q_c : out BIT -- q_c
);
END counter;
-- Architecture Declaration
ARCHITECTURE VST OF counter IS
COMPONENT a2_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT xr2_y
port (
i0 : in BIT; -- i0
i1 : in BIT; -- i1
t : out BIT; -- t
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT dffres
port (
input : in BIT; -- input
ck : in BIT; -- ck
reset : in BIT; -- reset
output : out BIT; -- output
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
SIGNAL c_1 : BIT; -- c_1
SIGNAL c_2 : BIT; -- c_2
SIGNAL c_3 : BIT; -- c_3
SIGNAL d_1 : BIT; -- d_1
SIGNAL d_2 : BIT; -- d_2
SIGNAL d_3 : BIT; -- d_3
SIGNAL d_4 : BIT; -- d_4
BEGIN
an00 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => c_1,
i1 => a(0),
i0 => e);
an01 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => c_2,
i1 => a(1),
i0 => c_1);
an02 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => c_3,
i1 => a(2),
i0 => c_2);
an03 : a2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => q_c,
i1 => a(3),
i0 => c_3);
xr00 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => d_1,
i1 => a(0),
i0 => e);
xr01 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => d_2,
i1 => a(1),
i0 => c_1);
xr02 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => d_3,
i1 => a(2),
i0 => c_2);
xr03 : xr2_y
PORT MAP (
vss => vss,
vdd => vdd,
t => d_4,
i1 => a(3),
i0 => c_3);
dff0 : dffres
PORT MAP (
vss => vss,
vdd => vdd,
output => a(0),
reset => res,
ck => ck,
input => d_1);
dff1 : dffres
PORT MAP (
vss => vss,
vdd => vdd,
output => a(1),
reset => res,
ck => ck,
input => d_2);
dff2 : dffres
PORT MAP (
vss => vss,
vdd => vdd,
output => a(3),
reset => res,
ck => ck,
input => d_3);
dff3 : dffres
PORT MAP (
vss => vss,
vdd => vdd,
output => a(4),
reset => res,
ck => ck,
input => d_4);
end VST;
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