Description

I2C is a two-wire, bidirectional serials bus that provide a simple, efficient method of data exchange between devices.
You can find I2C specification on Phillips web Site.
Work was originally started by Frédéric Renet. You can find his webpage here.

What you get

• WISHBONE rev.B2 compliant core
• No Multimaster operation
• No FIFO
• No slave mode
• Simple command based interface

Documentation

• Revision 0.4 of the WISHBONE I2C Master Core is available here.

Current status

• Design is available in VHDL and Verilog from OpenCores CVS via cvsweb or via cvsget
• Note that the Verilog version is currently up-to-date. The VHDL version needs some modifications.

Maintainer(s):

Richard Herveille

Mailing-list:

cores@opencores.org_NOSPAM